Subversion Repositories aes-128-ecb-encoder

##########################################################################
#
# Application : compile_simlib (2017.4)
# File name   : compile_simlib.log
#
# #########################################################################
INFO: [Vivado 12-5496] Finding simulator executables and checking version...
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...

Compiling libraries for 'ies' simulator in '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib'
--> Compiling 'verilog.secureip' library...
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip'
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip'

==============================================================================
BEGIN_COMPILATION_MESSAGES(ies:verilog:secureip)
ncvlog(64): 14.10-s005: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
DEFINE simprims_ver  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver
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ncvlog: *W,DLCPTH (./cds.lib,1): cds.lib Invalid path '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver' (cds.lib command ignored).
DEFINE xpm  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm
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ncvlog: *W,DLCPTH (./cds.lib,2): cds.lib Invalid path '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm' (cds.lib command ignored).
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/gtxe2_channel_fast/gtxe2_channel_fast_001.vp
        module secureip.GTXE2_CHANNEL_FAST_WRAP
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file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/gtxe2_channel_fast/gtxe2_channel_fast_002.vp
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file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_001.vp
        module secureip.GTXE2_CHANNEL_WRAP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/gtxe2_channel/gtxe2_channel_002.vp
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file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/gtxe2_common/gtxe2_common_001.vp
        module secureip.GTXE2_COMMON_WRAP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/gtxe2_common/gtxe2_common_002.vp
                errors: 0, warnings: 0
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file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/pcie_2_1/pcie_2_1_001.vp
        module secureip.PCIE_2_1_WRAP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/pcie_2_1/pcie_2_1_002.vp
                errors: 0, warnings: 0
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                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/iserdese2/iserdese2_001.vp
        module secureip.ISERDESE2_WRAP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/iserdese2/iserdese2_002.vp
        module secureip.B_ISERDESE2
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
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                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/oserdese2/oserdese2_001.vp
        module secureip.OSERDESE2_WRAP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/oserdese2/oserdese2_002.vp
        module secureip.B_OSERDESE2
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
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                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/in_fifo/in_fifo_001.vp
        module secureip.SIP_IN_FIFO
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/in_fifo/in_fifo_002.vp
                errors: 0, warnings: 0
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                errors: 0, warnings: 0
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/out_fifo/out_fifo_001.vp
        module secureip.SIP_OUT_FIFO
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/out_fifo/out_fifo_002.vp
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/phy_control/phy_control_001.vp
        module secureip.SIP_PHY_CONTROL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/phy_control/phy_control_002.vp
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/phaser_in/phaser_in_001.vp
        module secureip.SIP_PHASER_IN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/phaser_in/phaser_in_002.vp
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/phaser_out/phaser_out_001.vp
        module secureip.SIP_PHASER_OUT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip/phaser_out/phaser_out_002.vp
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
                errors: 0, warnings: 0
        Total errors/warnings found outside modules and primitives:
                errors: 0, warnings: 2

END_COMPILATION_MESSAGES(ies:verilog:secureip)
==============================================================================

    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip/.cxl.verilog.secureip.secureip.lin64.log'

compile_simlib[verilog.secureip]: 0 error(s), 2 warning(s), 33.33 % complete
--> Compiling 'verilog.simprim' library...
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims'
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver'

==============================================================================
BEGIN_COMPILATION_MESSAGES(ies:verilog:simprim)
ncvlog(64): 14.10-s005: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
DEFINE xpm  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm
|
ncvlog: *W,DLCPTH (./cds.lib,1): cds.lib Invalid path '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm' (cds.lib command ignored).
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BSCANE2.v
        module simprims_ver.BSCANE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_MULTIPLIER.v
        module simprims_ver.DSP_MULTIPLIER
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FDRE.v
        module simprims_ver.FDRE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTHE3_COMMON.v
        module simprims_ver.GTHE3_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTHE4_CHANNEL.v
        module simprims_ver.GTHE4_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFCTRL.v
        module simprims_ver.IBUFCTRL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_IBUFDISABLE_INT.v
        module simprims_ver.IBUFDS_IBUFDISABLE_INT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDELAYE2.v
        module simprims_ver.IDELAYE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDELAYE3.v
        module simprims_ver.IDELAYE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUF_ANALOG.v
        module simprims_ver.IOBUF_ANALOG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFT.v
        module simprims_ver.OBUFT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PHASER_IN.v
        module simprims_ver.PHASER_IN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PULLDOWN.v
        module simprims_ver.PULLDOWN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM32X1S.v
        module simprims_ver.RAM32X1S
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM64M8.v
        module simprims_ver.RAM64M8
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMS64E1.v
        module simprims_ver.RAMS64E1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/URAM288.v
        module simprims_ver.URAM288
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFG_GT_SYNC.v
        module simprims_ver.BUFG_GT_SYNC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFMR.v
        module simprims_ver.BUFMR
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/CFGLUT5.v
        module simprims_ver.CFGLUT5
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP48E1.v
        module simprims_ver.DSP48E1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP48E2.v
        module simprims_ver.DSP48E2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_M_DATA.v
        module simprims_ver.DSP_M_DATA
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/EFUSE_USR.v
        module simprims_ver.EFUSE_USR
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FE.v
        module simprims_ver.FE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FIFO18E1.v
        module simprims_ver.FIFO18E1
                errors: 0, warnings: 0
        module simprims_ver.FF18_INTERNAL_VLOG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GND.v
        module simprims_ver.GND
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTHE2_COMMON.v
        module simprims_ver.GTHE2_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTPE2_COMMON.v
        module simprims_ver.GTPE2_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/AND2B1L.v
        module simprims_ver.AND2B1L
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFHCE.v
        module simprims_ver.BUFHCE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/CARRY4.v
        module simprims_ver.CARRY4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/CARRY8.v
        module simprims_ver.CARRY8
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DCIRESET.v
        module simprims_ver.DCIRESET
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DCM_ADV.v
        module simprims_ver.DCM_ADV
                errors: 0, warnings: 0
        module simprims_ver.dcm_adv_clock_divide_by_2
                errors: 0, warnings: 0
        module simprims_ver.dcm_adv_maximum_period_check
                errors: 0, warnings: 0
        module simprims_ver.dcm_adv_clock_lost
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DCM_SP.v
        module simprims_ver.DCM_SP
                errors: 0, warnings: 0
        module simprims_ver.dcm_sp_clock_divide_by_2
                errors: 0, warnings: 0
        module simprims_ver.dcm_sp_maximum_period_check
                errors: 0, warnings: 0
        module simprims_ver.dcm_sp_clock_lost
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ICAPE2.v
        module simprims_ver.ICAPE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ICAPE3.v
        module simprims_ver.ICAPE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DIFFINBUF.v
        module simprims_ver.DIFFINBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DNA_PORT.v
        module simprims_ver.DNA_PORT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDDR_2CLK.v
        module simprims_ver.IDDR_2CLK
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DPHY_DIFFINBUF.v
        module simprims_ver.DPHY_DIFFINBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IN_FIFO.v
        module simprims_ver.IN_FIFO
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_C_DATA.v
        module simprims_ver.DSP_C_DATA
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LDCE.v
        module simprims_ver.LDCE
                errors: 0, warnings: 0
        primitive simprims_ver.latchsre_ldce
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FRAME_ECCE2.v
        module simprims_ver.FRAME_ECCE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FRAME_ECCE3.v
        module simprims_ver.FRAME_ECCE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FRAME_ECCE4.v
        module simprims_ver.FRAME_ECCE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTHE2_CHANNEL.v
        module simprims_ver.GTHE2_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MMCME4_BASE.v
        module simprims_ver.MMCME4_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTYE4_CHANNEL.v
        module simprims_ver.GTYE4_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTYE4_COMMON.v
        module simprims_ver.GTYE4_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MUXCY.v
        module simprims_ver.MUXCY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HBM_REF_CLK.v
        module simprims_ver.HBM_REF_CLK
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HBM_SNGLBLI_INTF_AXI.v
        module simprims_ver.HBM_SNGLBLI_INTF_AXI
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUF.v
        module simprims_ver.OBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFDS.v
        module simprims_ver.OBUFDS
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HBM_TWO_STACK_INTF.v
        module simprims_ver.HBM_TWO_STACK_INTF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFTDS_DCIEN.v
        module simprims_ver.OBUFTDS_DCIEN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_DIFF_OUT.v
        module simprims_ver.IBUFDS_DIFF_OUT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFT_DCIEN.v
        module simprims_ver.OBUFT_DCIEN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDDRE1.v
        module simprims_ver.IDDRE1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ILKNE4.v
        module simprims_ver.ILKNE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUF_DCIEN.v
        module simprims_ver.IOBUF_DCIEN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ODDRE1.v
        module simprims_ver.ODDRE1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUF_INTERMDISABLE.v
        module simprims_ver.IOBUF_INTERMDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OSERDESE1.v
        module simprims_ver.OSERDESE1
                errors: 0, warnings: 0
        module simprims_ver.selfheal_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.plg_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.rank12d_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.trif_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.txbuffer_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.fifo_tdpipe_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.fifo_reset_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.fifo_addr_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.iodlyctrl_npre_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.dout_oserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.tout_oserdese1_vlog
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OSERDESE2.v
        module simprims_ver.OSERDESE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OSERDESE3.v
        module simprims_ver.OSERDESE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PLLE2_ADV.v
        module simprims_ver.PLLE2_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PLLE4_BASE.v
        module simprims_ver.PLLE4_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PULLUP.v
        module simprims_ver.PULLUP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMB18E1.v
        module simprims_ver.RAMB18E1
                errors: 0, warnings: 0
        module simprims_ver.RB18_INTERNAL_VLOG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMB18E2.v
        module simprims_ver.RAMB18E2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT1.v
        module simprims_ver.LUT1
                errors: 0, warnings: 0
        primitive simprims_ver.x_lut1_mux2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMB36E1.v
        module simprims_ver.RAMB36E1
                errors: 0, warnings: 0
        module simprims_ver.RB36_INTERNAL_VLOG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT2.v
        module simprims_ver.LUT2
                errors: 0, warnings: 0
        primitive simprims_ver.x_lut2_mux4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMB36E2.v
        module simprims_ver.RAMB36E2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT3.v
        module simprims_ver.LUT3
                errors: 0, warnings: 0
        primitive simprims_ver.x_lut3_mux8
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMD64E.v
        module simprims_ver.RAMD64E
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMS32.v
        module simprims_ver.RAMS32
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT4.v
        module simprims_ver.LUT4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT5.v
        module simprims_ver.LUT5
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT6.v
        module simprims_ver.LUT6
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SRLC16E.v
        module simprims_ver.SRLC16E
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MMCME3_BASE.v
        module simprims_ver.MMCME3_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MMCME4_ADV.v
        module simprims_ver.MMCME4_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFDS_DPHY.v
        module simprims_ver.OBUFDS_DPHY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ODDR.v
        module simprims_ver.ODDR
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ODELAYE2.v
        module simprims_ver.ODELAYE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ODELAYE3.v
        module simprims_ver.ODELAYE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OR2L.v
        module simprims_ver.OR2L
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OSERDES.v
        module simprims_ver.OSERDES
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PCIE40E4.v
        module simprims_ver.PCIE40E4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PHASER_REF.v
        module simprims_ver.PHASER_REF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PHY_CONTROL.v
        module simprims_ver.PHY_CONTROL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PLLE4_ADV.v
        module simprims_ver.PLLE4_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PS8.v
        module simprims_ver.PS8
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM128X1D.v
        module simprims_ver.RAM128X1D
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM256X1S.v
        module simprims_ver.RAM256X1S
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM64X8SW.v
        module simprims_ver.RAM64X8SW
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMD32.v
        module simprims_ver.RAMD32
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RIU_OR.v
        module simprims_ver.RIU_OR
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SYSMONE4.v
        module simprims_ver.SYSMONE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/TX_BITSLICE.v
        module simprims_ver.TX_BITSLICE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/AUTOBUF.v
        module simprims_ver.AUTOBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFGP.v
        module simprims_ver.BUFGP
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/CAPTUREE2.v
        module simprims_ver.CAPTUREE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/INV.v
        module simprims_ver.INV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BITSLICE_CONTROL.v
        module simprims_ver.BITSLICE_CONTROL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFG.v
        module simprims_ver.BUFG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFH.v
        module simprims_ver.BUFH
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DNA_PORTE2.v
        module simprims_ver.DNA_PORTE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_A_B_DATA.v
        module simprims_ver.DSP_A_B_DATA
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FIFO36E2.v
        module simprims_ver.FIFO36E2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HARD_SYNC.v
        module simprims_ver.HARD_SYNC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HPIO_VREF.v
        module simprims_ver.HPIO_VREF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_DIFF_OUT_INTERMDISABLE.v
        module simprims_ver.IBUFDS_DIFF_OUT_INTERMDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_INTERMDISABLE_INT.v
        module simprims_ver.IBUFDS_INTERMDISABLE_INT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ILKN.v
        module simprims_ver.ILKN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDS_DIFF_OUT.v
        module simprims_ver.IOBUFDS_DIFF_OUT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDS_DIFF_OUT_DCIEN.v
        module simprims_ver.IOBUFDS_DIFF_OUT_DCIEN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/KEEPER.v
        module simprims_ver.KEEPER
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFDS_GTE4_ADV.v
        module simprims_ver.OBUFDS_GTE4_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFTDS.v
        module simprims_ver.OBUFTDS
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PCIE4CE4.v
        module simprims_ver.PCIE4CE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PLLE2_BASE.v
        module simprims_ver.PLLE2_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM64M.v
        module simprims_ver.RAM64M
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM64X1S.v
        module simprims_ver.RAM64X1S
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SIM_CONFIGE3.v
        module simprims_ver.SIM_CONFIGE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/XADC.v
        module simprims_ver.XADC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_PREADD_DATA.v
        module simprims_ver.DSP_PREADD_DATA
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUF.v
        module simprims_ver.IBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUF.v
        module simprims_ver.IOBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDS.v
        module simprims_ver.IOBUFDS
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFE3.v
        module simprims_ver.IOBUFE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFGCE_DIV.v
        module simprims_ver.BUFGCE_DIV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/CMACE4.v
        module simprims_ver.CMACE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_ALU.v
        module simprims_ver.DSP_ALU
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_PREADD.v
        module simprims_ver.DSP_PREADD
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FDCE.v
        module simprims_ver.FDCE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FIFO18E2.v
        module simprims_ver.FIFO18E2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FIFO36E1.v
        module simprims_ver.FIFO36E1
                errors: 0, warnings: 0
        module simprims_ver.FF36_INTERNAL_VLOG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTHE4_COMMON.v
        module simprims_ver.GTHE4_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTYE3_COMMON.v
        module simprims_ver.GTYE3_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LUT6_2.v
        module simprims_ver.LUT6_2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MMCME2_BASE.v
        module simprims_ver.MMCME2_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SIM_CONFIGE2.v
        module simprims_ver.SIM_CONFIGE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ZHOLD_DELAY.v
        module simprims_ver.ZHOLD_DELAY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PLLE3_ADV.v
        module simprims_ver.PLLE3_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM512X1S.v
        module simprims_ver.RAM512X1S
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM64X1D.v
        module simprims_ver.RAM64X1D
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/VCU.v
        module simprims_ver.VCU
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFCE_LEAF.v
        module simprims_ver.BUFCE_LEAF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFCE_ROW.v
        module simprims_ver.BUFCE_ROW
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFGCE.v
        module simprims_ver.BUFGCE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFG_GT.v
        module simprims_ver.BUFG_GT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFIO.v
        module simprims_ver.BUFIO
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FDPE.v
        module simprims_ver.FDPE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTHE3_CHANNEL.v
        module simprims_ver.GTHE3_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HBM_SNGLBLI_INTF_APB.v
        module simprims_ver.HBM_SNGLBLI_INTF_APB
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HSADC.v
        module simprims_ver.HSADC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_DIFF_OUT_IBUFDISABLE.v
        module simprims_ver.IBUFDS_DIFF_OUT_IBUFDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_IBUFDISABLE.v
        module simprims_ver.IBUFDS_IBUFDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_INTERMDISABLE.v
        module simprims_ver.IBUFDS_INTERMDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUF_ANALOG.v
        module simprims_ver.IBUF_ANALOG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUF_INTERMDISABLE.v
        module simprims_ver.IBUF_INTERMDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDELAYE2_FINEDELAY.v
        module simprims_ver.IDELAYE2_FINEDELAY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDSE3.v
        module simprims_ver.IOBUFDSE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDS_DCIEN.v
        module simprims_ver.IOBUFDS_DCIEN
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ISERDESE1.v
        module simprims_ver.ISERDESE1
                errors: 0, warnings: 0
        module simprims_ver.bscntrl_iserdese1_vlog
                errors: 0, warnings: 0
        module simprims_ver.ice_iserdese1_vlog
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ISERDESE2.v
        module simprims_ver.ISERDESE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ISERDESE3.v
        module simprims_ver.ISERDESE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MUXF7.v
        module simprims_ver.MUXF7
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MUXF8.v
        module simprims_ver.MUXF8
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MUXF9.v
        module simprims_ver.MUXF9
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFDS_GTE3.v
        module simprims_ver.OBUFDS_GTE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFDS_GTE4.v
        module simprims_ver.OBUFDS_GTE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ODELAYE2_FINEDELAY.v
        module simprims_ver.ODELAYE2_FINEDELAY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PHASER_OUT.v
        module simprims_ver.PHASER_OUT
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PHASER_OUT_PHY.v
        module simprims_ver.PHASER_OUT_PHY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PLLE3_BASE.v
        module simprims_ver.PLLE3_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PS7.v
        module simprims_ver.PS7
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM256X1D.v
        module simprims_ver.RAM256X1D
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM32M16.v
        module simprims_ver.RAM32M16
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM32X1D.v
        module simprims_ver.RAM32X1D
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAMS64E.v
        module simprims_ver.RAMS64E
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RXTX_BITSLICE.v
        module simprims_ver.RXTX_BITSLICE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SRL16E.v
        module simprims_ver.SRL16E
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/STARTUPE2.v
        module simprims_ver.STARTUPE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/STARTUPE3.v
        module simprims_ver.STARTUPE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SYSMONE1.v
        module simprims_ver.SYSMONE1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/TX_BITSLICE_TRI.v
        module simprims_ver.TX_BITSLICE_TRI
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/VCC.v
        module simprims_ver.VCC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFGCTRL.v
        module simprims_ver.BUFGCTRL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFR.v
        module simprims_ver.BUFR
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDELAYCTRL.v
        module simprims_ver.IDELAYCTRL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDS_DIFF_OUT_INTERMDISABLE.v
        module simprims_ver.IOBUFDS_DIFF_OUT_INTERMDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/LDPE.v
        module simprims_ver.LDPE
                errors: 0, warnings: 0
        primitive simprims_ver.latchsre_ldpe
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MMCME3_ADV.v
        module simprims_ver.MMCME3_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RX_BITSLICE.v
        module simprims_ver.RX_BITSLICE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/USR_ACCESSE2.v
        module simprims_ver.USR_ACCESSE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/XORCY.v
        module simprims_ver.XORCY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUF.v
        module simprims_ver.BUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFG_PS.v
        module simprims_ver.BUFG_PS
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BUFMRCE.v
        module simprims_ver.BUFMRCE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/CMAC.v
        module simprims_ver.CMAC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/FDSE.v
        module simprims_ver.FDSE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTPE2_CHANNEL.v
        module simprims_ver.GTPE2_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTXE2_CHANNEL.v
        module simprims_ver.GTXE2_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTXE2_COMMON.v
        module simprims_ver.GTXE2_COMMON
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/GTYE3_CHANNEL.v
        module simprims_ver.GTYE3_CHANNEL
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HBM_ONE_STACK_INTF.v
        module simprims_ver.HBM_ONE_STACK_INTF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/HSDAC.v
        module simprims_ver.HSDAC
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_DPHY.v
        module simprims_ver.IBUFDS_DPHY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IDDR.v
        module simprims_ver.IDDR
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/INBUF.v
        module simprims_ver.INBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ISERDES.v
        module simprims_ver.ISERDES
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MASTER_JTAG.v
        module simprims_ver.MASTER_JTAG
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/MMCME2_ADV.v
        module simprims_ver.MMCME2_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OBUFDS_GTE3_ADV.v
        module simprims_ver.OBUFDS_GTE3_ADV
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/OUT_FIFO.v
        module simprims_ver.OUT_FIFO
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PHASER_IN_PHY.v
        module simprims_ver.PHASER_IN_PHY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM128X1S.v
        module simprims_ver.RAM128X1S
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/RAM32M.v
        module simprims_ver.RAM32M
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/SRLC32E.v
        module simprims_ver.SRLC32E
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/URAM288_BASE.v
        module simprims_ver.URAM288_BASE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/BIBUF.v
        module simprims_ver.BIBUF
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IOBUFDS_INTERMDISABLE.v
        module simprims_ver.IOBUFDS_INTERMDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/JTAG_SIME2.v
        module simprims_ver.JTAG_SIME2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS.v
        module simprims_ver.IBUFDS
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDSE3.v
        module simprims_ver.IBUFDSE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_GTE2.v
        module simprims_ver.IBUFDS_GTE2
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_GTE3.v
        module simprims_ver.IBUFDS_GTE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFDS_GTE4.v
        module simprims_ver.IBUFDS_GTE4
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUFE3.v
        module simprims_ver.IBUFE3
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/IBUF_IBUFDISABLE.v
        module simprims_ver.IBUF_IBUFDISABLE
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/ISERDES_NODELAY.v
        module simprims_ver.ISERDES_NODELAY
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PCIE_3_0.v
        module simprims_ver.PCIE_3_0
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PCIE_3_1.v
        module simprims_ver.PCIE_3_1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/PCIE_2_1.v
        module simprims_ver.PCIE_2_1
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims/DSP_OUTPUT.v
        module simprims_ver.DSP_OUTPUT
                errors: 0, warnings: 0
        Total errors/warnings found outside modules and primitives:
                errors: 0, warnings: 1

END_COMPILATION_MESSAGES(ies:verilog:simprim)
==============================================================================

    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver/.cxl.verilog.simprim.simprims_ver.lin64.log'

compile_simlib[verilog.simprim]: 0 error(s), 1 warning(s), 66.67 % complete
--> Compiling 'verilog.xpm' library...
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm'
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm'

==============================================================================
BEGIN_COMPILATION_MESSAGES(ies:verilog:xpm)
ncvlog(64): 14.10-s005: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv
        module xpm.xpm_cdc_single
                errors: 0, warnings: 0
        module xpm.xpm_cdc_gray
                errors: 0, warnings: 0
        module xpm.xpm_cdc_handshake
                errors: 0, warnings: 0
        module xpm.xpm_cdc_pulse
                errors: 0, warnings: 0
        module xpm.xpm_cdc_array_single
                errors: 0, warnings: 0
        module xpm.xpm_cdc_sync_rst
                errors: 0, warnings: 0
        module xpm.xpm_cdc_async_rst
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/simulation/xpm_fifo_tb.sv
        module xpm.xpm_fifo_tb
                errors: 0, warnings: 0
        module xpm.xpm_fifo_ex
                errors: 0, warnings: 0
        module xpm.xpm_fifo_gen_dverif
                errors: 0, warnings: 0
        module xpm.xpm_fifo_gen_rng
                errors: 0, warnings: 0
        module xpm.xpm_fifo_gen_dgen
                errors: 0, warnings: 0
        module xpm.xpm_fifo_gen_pctrl
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv
        module xpm.xpm_fifo_base
                errors: 0, warnings: 0
        module xpm.xpm_fifo_rst
                errors: 0, warnings: 0
        module xpm.xpm_counter_updn
                errors: 0, warnings: 0
        module xpm.xpm_fifo_reg_vec
                errors: 0, warnings: 0
        module xpm.xpm_fifo_reg_bit
                errors: 0, warnings: 0
        module xpm.xpm_reg_pipe_bit
                errors: 0, warnings: 0
        module xpm.xpm_fifo_sync
                errors: 0, warnings: 0
        module xpm.xpm_fifo_async
                errors: 0, warnings: 0
        module xpm.xpm_fifo_axis
                errors: 0, warnings: 0
file: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
        module xpm.xpm_memory_base
                errors: 0, warnings: 0
        module xpm.asym_bwe_bb
                errors: 0, warnings: 0
        module xpm.xpm_memory_dpdistram
                errors: 0, warnings: 0
        module xpm.xpm_memory_dprom
                errors: 0, warnings: 0
        module xpm.xpm_memory_sdpram
                errors: 0, warnings: 0
        module xpm.xpm_memory_spram
                errors: 0, warnings: 0
        module xpm.xpm_memory_sprom
                errors: 0, warnings: 0
        module xpm.xpm_memory_tdpram
                errors: 0, warnings: 0

END_COMPILATION_MESSAGES(ies:verilog:xpm)
==============================================================================

    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm/.cxl.verilog.xpm.xpm.lin64.log'

compile_simlib[verilog.xpm]: 0 error(s), 0 warning(s), 100.00 % complete
Copying setup file 'cds.lib' to '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/cds.lib' ...

********************************************************************************************
*                                  COMPILATION SUMMARY                                     *
*                                                                                          *
*  Simulator used: ies                                                                     *
*  Compiled on: Tue Jul 28 09:51:19 2020                                                   *
*                                                                                          *
********************************************************************************************
*  Library                        | Language | Mapped Library Name | Error(s) | Warning(s) *
*------------------------------------------------------------------------------------------*
*  secureip                       | verilog  | secureip            | 0        | 2          *
*------------------------------------------------------------------------------------------*
*  simprim                        | verilog  | simprims_ver        | 0        | 1          *
*------------------------------------------------------------------------------------------*
*  xpm                            | verilog  | xpm                 | 0        | 0          *
*------------------------------------------------------------------------------------------*