Subversion Repositories aes-128-ecb-encoder

#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Thu Jul 30 13:33:37 2020
# Process ID: 8661
# Current directory: /home/user/aes128/fpga/aes128_ecb_2017
# Command line: vivado
# Log file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.log
# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
update_compile_order -fileset sources_1
open_run impl_1
INFO: [Netlist 29-17] Analyzing 920 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_board.xdc]
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_board.xdc]
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_early.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 6946.168 ; gain = 540.656 ; free physical = 2369 ; free virtual = 7494
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_early.xdc]
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap.xdc]
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6951.168 ; gain = 5.000 ; free physical = 2364 ; free virtual = 7489
Restored from archive | CPU: 0.170000 secs | Memory: 4.382431 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6951.168 ; gain = 5.000 ; free physical = 2364 ; free virtual = 7489
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:00:30 ; elapsed = 00:00:41 . Memory (MB): peak = 7149.465 ; gain = 1021.266 ; free physical = 2265 ; free virtual = 7384
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.4
  **** Build date : Dec 15 2017-21:02:11
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 7149.465 ; gain = 0.000 ; free physical = 2204 ; free virtual = 7334
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601.
Check cable connectivity and that the target board is powered up then
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
disconnect_hw_server localhost:3121
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 7149.465 ; gain = 0.000 ; free physical = 2202 ; free virtual = 7330
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
current_hw_device [get_hw_devices xc7k325t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7k325t_0] 0]
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {28f00ap30t-bpi-x16}] 0]
set_property PROBES.FILE {} [get_hw_devices xc7k325t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7k325t_0]
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
program_hw_devices -disable_eos_check [get_hw_devices xc7k325t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 7621.066 ; gain = 0.000 ; free physical = 1704 ; free virtual = 6833
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Jul 30 13:52:01 2020] Launched synth_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
[Thu Jul 30 13:52:01 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.4
  **** Build date : Dec 15 2017-21:02:11
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
current_hw_device [get_hw_devices xc7k325t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7k325t_0] 0]
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {28f00ap30t-bpi-x16}] 0]
set_property PROBES.FILE {} [get_hw_devices xc7k325t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7k325t_0]
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
program_hw_devices [get_hw_devices xc7k325t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 7720.871 ; gain = 0.000 ; free physical = 3185 ; free virtual = 6778
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
close_design
close_project
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
update_compile_order -fileset sources_1
close_project
create_project uart_lb_test /home/user/aes128/fpga/uart_lb_test -part xc7k325tffg900-2
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
set_property board_part xilinx.com:kc705:part0:1.5 [current_project]
close [ open /home/user/aes128/fpga/uart_lb_test/src/top_wrap.v w ]
add_files /home/user/aes128/fpga/uart_lb_test/src/top_wrap.v
update_compile_order -fileset sources_1
file mkdir /home/user/aes128/fpga/uart_lb_test/uart_lb_test.srcs/constrs_1
close [ open /home/user/aes128/fpga/uart_lb_test/uart_lb_test.srcs/constrs_1/pinout.sdc w ]
add_files -fileset constrs_1 /home/user/aes128/fpga/uart_lb_test/uart_lb_test.srcs/constrs_1/pinout.sdc
launch_runs impl_1 -jobs 2
[Thu Jul 30 14:10:31 2020] Launched synth_1...
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/synth_1/runme.log
[Thu Jul 30 14:10:31 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Jul 30 14:13:11 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
reset_run impl_1 -prev_step 
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Jul 30 14:16:51 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
open_run impl_1
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp3/top_wrap.xdc]
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp3/top_wrap.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 3169 ; free virtual = 6792
Restored from archive | CPU: 0.000000 secs | Memory: 0.015068 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 3169 ; free virtual = 6792
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Jul 30 14:20:03 2020] Launched synth_1...
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/synth_1/runme.log
[Thu Jul 30 14:20:03 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
close_project
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
update_compile_order -fileset sources_1
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.4
  **** Build date : Dec 15 2017-21:02:11
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
current_hw_device [get_hw_devices xc7k325t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7k325t_0] 0]
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {28f00ap30t-bpi-x16}] 0]
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
reset_run impl_1 -prev_step 
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Jul 30 15:31:01 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
write_cfgmem  -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs"
Command: write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs
Creating config memory files...
INFO: [Writecfgmem 68-23] Start address provided has been multiplied by a factor of 2 due to the use of interface BPIX16.
Creating bitstream load up from address 0x00000000
Loading bitfile /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
Writing file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs
Writing log file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.prm
===================================
Configuration Memory information
===================================
File Format        MCS
Interface          BPIX16
Size               128M
Start Address      0x00000000
End Address        0x07FFFFFF

Addr1         Addr2         Date                    File(s)
0x00000000    0x00AE9D9B    Jul 30 15:32:06 2020    /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
set_property PROGRAM.ADDRESS_RANGE  {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.FILES [list "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.PRM_FILE {} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.BPI_RS_PINS {none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
startgroup 
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE  [lindex [get_hw_devices xc7k325t_0] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]]]] }  { create_hw_bitstream -hw_device [lindex [get_hw_devices xc7k325t_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7k325t_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7k325t_0] 0]; }; 
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 2434 ; free virtual = 6398
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
Mfg ID : 89   Memory Type : 8962   Memory Capacity : 0   Device ID 1 : 0   Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Program and Verify Operations...
Program/Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:14 ; elapsed = 00:04:28 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 2427 ; free virtual = 6380
endgroup
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
exit
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 15:42:17 2020...