Subversion Repositories aes-128-ecb-encoder

#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Wed Jul 29 15:27:30 2020
# Process ID: 2077
# Current directory: /home/user/aes/fpga/aec128_ecb_2017
# Command line: vivado
# Log file: /home/user/aes/fpga/aec128_ecb_2017/vivado.log
# Journal file: /home/user/aes/fpga/aec128_ecb_2017/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 6033.367 ; gain = 52.977 ; free physical = 4968 ; free virtual = 8475
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 2
[Wed Jul 29 15:29:53 2020] Launched synth_1...
Run output will be captured here: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
launch_runs impl_1 -jobs 2
[Wed Jul 29 15:33:07 2020] Launched impl_1...
Run output will be captured here: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
open_run impl_1
INFO: [Netlist 29-17] Analyzing 911 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_board.xdc]
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_board.xdc]
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_early.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 6913.031 ; gain = 550.430 ; free physical = 4069 ; free virtual = 7687
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_early.xdc]
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap.xdc]
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6918.031 ; gain = 5.000 ; free physical = 4064 ; free virtual = 7683
Restored from archive | CPU: 0.160000 secs | Memory: 4.181816 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6918.031 ; gain = 5.000 ; free physical = 4064 ; free virtual = 7683
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 7091.215 ; gain = 986.719 ; free physical = 3984 ; free virtual = 7596
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Wed Jul 29 15:36:50 2020] Launched impl_1...
Run output will be captured here: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
write_cfgmem  -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file "/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.mcs"
Command: write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.mcs
Creating config memory files...
INFO: [Writecfgmem 68-23] Start address provided has been multiplied by a factor of 2 due to the use of interface BPIX16.
Creating bitstream load up from address 0x00000000
Loading bitfile /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
Writing file /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.mcs
Writing log file /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.prm
===================================
Configuration Memory information
===================================
File Format        MCS
Interface          BPIX16
Size               128M
Start Address      0x00000000
End Address        0x07FFFFFF

Addr1         Addr2         Date                    File(s)
0x00000000    0x00AE9D9B    Jul 29 15:37:54 2020    /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.4
  **** Build date : Dec 15 2017-21:02:11
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
 Targets(s) ", jsn1" may be locked by another hw_server.
disconnect_hw_server localhost:3121
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
 Targets(s) ", jsn1jsn2jsn3jsn4jsn5jsn6jsn7jsn8jsn9jsn10" may be locked by another hw_server.
exit
INFO: [Common 17-206] Exiting Vivado at Wed Jul 29 15:45:15 2020...