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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [vivado_28010.backup.jou] - Rev 2
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#-----------------------------------------------------------# Vivado v2017.4 (64-bit)# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017# Start of session at: Thu Jul 30 09:54:46 2020# Process ID: 28010# Current directory: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017# Command line: vivado# Log file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.log# Journal file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.jou#-----------------------------------------------------------start_guiopen_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xprupdate_compile_order -fileset sources_1open_run impl_1write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.vwrite_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdfreport_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1close_designopen_run synth_1 -name synth_1save_constraintsreset_run synth_1launch_runs synth_1 -jobs 16wait_on_run synth_1refresh_designcreate_generated_clock -name clk_gen -source [get_pins clkgen/clk_in1_p] -divide_by 2 -add -master_clock [get_clocks CLK_IN_P] [get_pins clkgen/clk_out1]save_constraintsset_input_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_rx]set_output_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_tx]save_constraintsreset_run synth_1launch_runs synth_1 -jobs 16wait_on_run synth_1close_designopen_run synth_1 -name synth_1launch_runs impl_1 -jobs 16wait_on_run impl_1close_designopen_run impl_1report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.vwrite_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdfclose_designreset_run synth_1launch_runs impl_1 -jobs 16wait_on_run impl_1open_run impl_1report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.vwrite_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf