Subversion Repositories aes-128-ecb-encoder

#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Thu Jul 30 12:59:24 2020
# Process ID: 5806
# Current directory: /home/user/aes128/fpga/aes128_ecb_2017
# Command line: vivado
# Log file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.log
# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
INFO: [Project 1-313] Project file moved from '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 6028.020 ; gain = 32.262 ; free physical = 2166 ; free virtual = 8341
update_compile_order -fileset sources_1
reset_run impl_1
launch_runs impl_1 -jobs 2
[Thu Jul 30 13:01:29 2020] Launched clk_gen_synth_1, axi_uartlite_module_synth_1, synth_1...
Run output will be captured here:
clk_gen_synth_1: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/runme.log
axi_uartlite_module_synth_1: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/runme.log
synth_1: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
[Thu Jul 30 13:01:29 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
reset_run synth_1
launch_runs synth_1 -jobs 2
[Thu Jul 30 13:13:35 2020] Launched synth_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
launch_runs impl_1 -jobs 2
[Thu Jul 30 13:18:19 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
open_run impl_1
INFO: [Netlist 29-17] Analyzing 920 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_board.xdc]
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_board.xdc]
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_early.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 6947.934 ; gain = 551.656 ; free physical = 2456 ; free virtual = 7532
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap_early.xdc]
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap.xdc]
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-5806-orme22/dcp6/aes128_ecb_fpga_wrap.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6952.934 ; gain = 5.000 ; free physical = 2451 ; free virtual = 7528
Restored from archive | CPU: 0.170000 secs | Memory: 4.383476 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6952.934 ; gain = 5.000 ; free physical = 2451 ; free virtual = 7528
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:00:28 ; elapsed = 00:00:42 . Memory (MB): peak = 7123.285 ; gain = 941.883 ; free physical = 2362 ; free virtual = 7436
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
launch_runs impl_1 -to_step write_bitstream -jobs 2
[Thu Jul 30 13:22:05 2020] Launched impl_1...
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.4
  **** Build date : Dec 15 2017-21:02:11
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
 Targets(s) ", jsn1" may be locked by another hw_server.
disconnect_hw_server localhost:3121
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
 Targets(s) ", jsn1jsn2jsn3jsn4" may be locked by another hw_server.
refresh_hw_server {localhost:3121}
WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121]
Check to make sure the cable targets connected to this machine are properly connected
and powered up, then use the refresh_hw_server command to re-register the hardware targets.
refresh_hw_server {localhost:3121}
WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121]
Check to make sure the cable targets connected to this machine are properly connected
and powered up, then use the refresh_hw_server command to re-register the hardware targets.
refresh_hw_server {localhost:3121}
WARNING: [Labtoolstcl 44-27] No hardware targets exist on the server [localhost:3121]
Check to make sure the cable targets connected to this machine are properly connected
and powered up, then use the refresh_hw_server command to re-register the hardware targets.
exit
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:32:52 2020...