Subversion Repositories aes-128-ecb-encoder

/*

Xilinx Vivado v2017.4 (64-bit) [Major: 2017, Minor: 4]
SW Build: 2086221 on Fri Dec 15 20:54:30 MST 2017
IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017

Process ID: 28010
License: Customer

Current time:   Thu Jul 30 09:55:06 MSK 2020
Time zone:      Moscow Standard Time (W-SU)

OS: Red Hat Enterprise Linux Server release 6.9 (Santiago)
OS Version: 2.6.32-696.el6.x86_64
OS Architecture: amd64
Available processors (cores): 32

Display: :3.0
Screen size: 2500x1300
Screen resolution (DPI): 96
Available screens: 1
Available disk space: 41 GB
Default font: family=Dialog,name=Dialog,style=plain,size=12

Java version:   1.8.0_112 64-bit
Java home:      /opt/cad/xilinx/Vivado2017/Vivado/2017.4/tps/lnx64/jre
JVM executable location:        /opt/cad/xilinx/Vivado2017/Vivado/2017.4/tps/lnx64/jre/bin/java

User name:      v.gulyaev
User home directory: /home/v.gulyaev
User working directory: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017
User country:   US
User language:  en
User locale:    en_US

RDI_BASEROOT: /opt/cad/xilinx/Vivado2017/Vivado
HDI_APPROOT: /opt/cad/xilinx/Vivado2017/Vivado/2017.4
RDI_DATADIR: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/data
RDI_BINDIR: /opt/cad/xilinx/Vivado2017/Vivado/2017.4/bin

Vivado preferences file location: /home/v.gulyaev/.Xilinx/Vivado/2017.4/vivado.xml
Vivado preferences directory: /home/v.gulyaev/.Xilinx/Vivado/2017.4/
Vivado layouts directory: /home/v.gulyaev/.Xilinx/Vivado/2017.4/layouts
PlanAhead jar file location:    /opt/cad/xilinx/Vivado2017/Vivado/2017.4/lib/classes/planAhead.jar
Vivado log file location:       /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.log
Vivado journal file location:   /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/vivado.jou
Engine tmp dir:         ./.Xil/Vivado-28010-gigant.modulew.local

GUI allocated memory:   167 MB
GUI max memory:         3,052 MB
Engine allocated memory: 5,046 MB

Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

*/

// TclEventType: START_GUI
// Tcl Message: start_gui 
selectMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // U (q, cj)
// [GUI Memory]: 59 MB (+59555kb) [00:00:06]
// [Engine Memory]: 5,046 MB (+5139737kb) [00:00:06]
dismissMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // U (q, cj)
selectMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // U (q, cj)
dismissMenu(PAResourceItoN.MainMenuMgr_FLOW, "Flow"); // U (q, cj)
// HMemoryUtils.trashcanNow. Engine heap size: 5,056 MB. GUI used memory: 38 MB. Current time: 7/30/20 9:55:08 AM MSK
// Elapsed time: 11 seconds
selectList(PAResourceQtoS.SyntheticaGettingStartedView_RECENT_PROJECTS, "/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr", 0); // q (O, cj)
// Opening Vivado Project: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr. Version: Vivado v2017.4 
// bs (cj):  Open Project : addNotify
// TclEventType: DEBUG_PROBE_SET_CHANGE
// Tcl Message: open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr 
// TclEventType: MSGMGR_MOVEMSG
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: FILE_SET_NEW
// TclEventType: RUN_COMPLETED
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: RUN_COMPLETED
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: RUN_CURRENT
// TclEventType: FILE_SET_CHANGE
// TclEventType: PROJECT_NEW
// [GUI Memory]: 65 MB (+3169kb) [00:00:26]
// [GUI Memory]: 71 MB (+2265kb) [00:00:27]
// Tcl Message: open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr 
// Tcl Message: Scanning sources... Finished scanning sources 
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip'. 
// HMemoryUtils.trashcanNow. Engine heap size: 5,189 MB. GUI used memory: 50 MB. Current time: 7/30/20 9:55:26 AM MSK
// Tcl Message: open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 6310.867 ; gain = 89.688 ; free physical = 59919 ; free virtual = 99507 
// Project name: aes128_ecb; location: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017; part: xc7k325tffg900-2
dismissDialog("Open Project"); // bs (cj)
// TclEventType: DG_ANALYSIS_MSG_RESET
// TclEventType: DG_GRAPH_GENERATED
// Tcl Message: update_compile_order -fileset sources_1 
// Elapsed time: 28 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 18, true); // u (O, cj) - Node
// Run Command: PAResourceCommand.PACommandNames_GOTO_IMPLEMENTED_DESIGN
// bs (cj):  Open Implemented Design : addNotify
// Tcl Message: open_run impl_1 
// HMemoryUtils.trashcanNow. Engine heap size: 5,263 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:56:03 AM MSK
// [Engine Memory]: 5,306 MB (+7522kb) [00:01:26]
// HMemoryUtils.trashcanNow. Engine heap size: 5,339 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:56:28 AM MSK
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: POWER_CNS_STALE
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// HMemoryUtils.trashcanNow. Engine heap size: 5,557 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:56:48 AM MSK
// [Engine Memory]: 5,585 MB (+14974kb) [00:01:55]
// HMemoryUtils.trashcanNow. Engine heap size: 5,758 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:57:03 AM MSK
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: DESIGN_NEW
// HMemoryUtils.trashcanNow. Engine heap size: 6,039 MB. GUI used memory: 49 MB. Current time: 7/30/20 9:57:08 AM MSK
// [Engine Memory]: 6,040 MB (+183600kb) [00:02:09]
// TclEventType: DESIGN_NEW
// [GUI Memory]: 81 MB (+6786kb) [00:02:10]
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
// [GUI Memory]: 87 MB (+2249kb) [00:02:12]
// Device: addNotify
// [GUI Memory]: 91 MB (+133kb) [00:02:13]
// DeviceView Instantiated
// TclEventType: CURR_DESIGN_SET
// Tcl Message: INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Project 1-570] Preparing netlist for logic optimization 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_board.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_board.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_early.xdc] 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] 
// Tcl Message: get_clocks: Time (s): cpu = 00:00:20 ; elapsed = 00:00:37 . Memory (MB): peak = 7178.695 ; gain = 594.926 ; free physical = 59179 ; free virtual = 98775 
// Tcl Message: Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap_early.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp0/aes128_ecb_fpga_wrap.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. 
// Tcl Message: Read XDEF File: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 7183.691 ; gain = 4.000 ; free physical = 59174 ; free virtual = 98770 
// Tcl Message: Restored from archive | CPU: 0.220000 secs | Memory: 4.244667 MB | 
// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 7183.691 ; gain = 4.000 ; free physical = 59174 ; free virtual = 98770 
// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
// [GUI Memory]: 97 MB (+1637kb) [00:02:14]
// Tcl Message: open_run: Time (s): cpu = 00:00:52 ; elapsed = 00:01:17 . Memory (MB): peak = 7467.965 ; gain = 1118.707 ; free physical = 59003 ; free virtual = 98593 
// ExpRunCommands.openImplResults elapsed time: 77s
// TclEventType: DRC_ADDED
// Device view-level: 0.0
// [GUI Memory]: 107 MB (+4908kb) [00:02:15]
// RouteApi: Init Delay Mediator Swing Worker Finished
// TclEventType: DRC_ADDED
// TclEventType: METHODOLOGY_ADDED
// TclEventType: POWER_UPDATED
// [GUI Memory]: 116 MB (+3705kb) [00:02:16]
// [GUI Memory]: 123 MB (+1093kb) [00:02:16]
// [GUI Memory]: 129 MB (+270kb) [00:02:16]
// TclEventType: TIMING_SUMMARY_UPDATED
// 'dO' command handler elapsed time: 81 seconds
// Elapsed time: 81 seconds
dismissDialog("Open Implemented Design"); // bs (cj)
// [GUI Memory]: 137 MB (+1565kb) [00:02:18]
// [GUI Memory]: 146 MB (+2271kb) [00:02:19]
// Elapsed time: 36 seconds
selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aF (Q, cj)
// Elapsed time: 18 seconds
selectTree(PAResourceItoN.NetlistTreeView_NETLIST_TREE, "[aes128_ecb_fpga_wrap]", 0, true); // aW (O, cj) - Node
selectTree(PAResourceItoN.NetlistTreeView_NETLIST_TREE, "[aes128_ecb_fpga_wrap]", 0, true, false, false, false, false, true); // aW (O, cj) - Double Click - Node
// Run Command: PAResourceCommand.PACommandNames_GOTO_DEFINITION
// Tcl Command: 'rdi::info_commands {w*}'
// Tcl Command: 'rdi::info_commands {wri*}'
// Tcl Command: 'rdi::info_commands {write*}'
// Tcl Command: 'rdi::info_commands {write_*}'
// Tcl Command: 'rdi::info_commands {write_v*}'
// Elapsed time: 14 seconds
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_v", true); // aF (ae, cj)
// Tcl Command: 'rdi::match_options {write_verilog} {}'
// Tcl Command: 'rdi::match_options {write_verilog} {fo}'
// Tcl Command: 'rdi::match_options {write_verilog} {for}'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -for", true); // aF (ae, cj)
// Tcl Command: 'rdi::match_options {write_verilog} {}'
// Tcl Command: 'rdi::match_options {write_verilog} {m}'
// Tcl Command: 'rdi::match_options {write_verilog} {mo}'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mo", true); // aF (ae, cj)
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./ne", true); // aF (ae, cj)
// Tcl Command: 'rdi::info_commands bd::match_path'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/", true); // aF (ae, cj)
applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v"); // aF (ae, cj)
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
// Tcl Message: write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.v 
// Tcl Command: 'rdi::info_commands {write_*}'
// Tcl Command: 'rdi::info_commands {write_*}'
// Tcl Command: 'rdi::info_commands {write_s*}'
// Tcl Command: 'rdi::info_commands {write_sd*}'
// Tcl Command: 'rdi::info_commands {write_sdf*}'
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
// Elapsed time: 18 seconds
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.s", true); // aF (ae, cj)
applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf"); // aF (ae, cj)
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
// Tcl Message: write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf 
// bs (cj):  Tcl Command Line : addNotify
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.sdf 
dismissDialog("Tcl Command Line"); // bs (cj)
// TclEventType: DG_GRAPH_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DG_ANALYSIS_MSG_RESET
// TclEventType: DG_GRAPH_GENERATED
// HMemoryUtils.trashcanNow. Engine heap size: 6,261 MB. GUI used memory: 101 MB. Current time: 7/30/20 10:27:08 AM MSK
// Elapsed time: 2506 seconds
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
// Elapsed time: 33 seconds
selectTab((HResource) null, (HResource) null, "Sources", 0); // aF (Q, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 4); // B (D, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 5); // B (D, cj)
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i (N, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module]", 1, true); // B (D, cj) - Node
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module]", 1); // B (D, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, Synthesis]", 3); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, axi_uartlite_module_sim_netlist.v]", 15, false); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, axi_uartlite_module_sim_netlist.v]", 15, false, false, false, false, false, true); // B (D, cj) - Double Click
// Elapsed time: 12 seconds
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 21, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
// aF (cj): Report Timing Summary: addNotify
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (aF)
dismissDialog("Report Timing Summary"); // aF (cj)
// bs (cj):  Report Timing Summary : addNotify
// TclEventType: TIMING_RESULTS_STALE
// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 
// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs 
// TclEventType: TIMING_SUMMARY_UPDATED
// [GUI Memory]: 156 MB (+2909kb) [00:47:28]
dismissDialog("Report Timing Summary"); // bs (cj)
// Elapsed time: 18 seconds
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 5); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 7); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Setup 0.877 ns]", 8, false); // a (O, cj)
selectTableHeader(PAResourceTtoZ.TimingItemFlatTablePanel_TABLE, "From", 4); // i (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Hold 0.094 ns]", 9, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 7, true); // a (O, cj) - Node
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Setup 0.877 ns]", 8, false); // a (O, cj)
collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
// Run Command: PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN
// e (cj): Close Design: addNotify
selectButton(PAResourceAtoD.ClosePlanner_YES, "Yes"); // a (e)
// TclEventType: DESIGN_CLOSE
// HMemoryUtils.trashcanNow. Engine heap size: 6,275 MB. GUI used memory: 86 MB. Current time: 7/30/20 10:43:21 AM MSK
// TclEventType: TIMING_RESULTS_UNLOAD
// Engine heap size: 6,275 MB. GUI used memory: 87 MB. Current time: 7/30/20 10:43:21 AM MSK
// TclEventType: CURR_DESIGN_SET
// TclEventType: DESIGN_CLOSE
// bi (cj): Synthesis is Out-of-date: addNotify
// Tcl Message: close_design 
dismissDialog("Close Design"); // e (cj)
selectButton(PAResourceQtoS.StaleRunDialog_OPEN_DESIGN, "Open Design"); // a (bi)
// bs (cj):  Open Synthesized Design : addNotify
dismissDialog("Synthesis is Out-of-date"); // bi (cj)
// Tcl Message: open_run synth_1 -name synth_1 
// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7k325tffg900-2 
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: POWER_CNS_STALE
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: FLOORPLAN_MODIFY
// TclEventType: DESIGN_NEW
// HMemoryUtils.trashcanNow. Engine heap size: 6,340 MB. GUI used memory: 60 MB. Current time: 7/30/20 10:43:29 AM MSK
// TclEventType: DESIGN_NEW
// [Engine Memory]: 6,345 MB (+3453kb) [00:48:30]
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
// Device: addNotify
// DeviceView Instantiated
// TclEventType: CURR_DESIGN_SET
// Tcl Message: INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen' INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite' INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst' 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] 
// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
// Device view-level: 0.0
// RouteApi: Init Delay Mediator Swing Worker Finished
// 'dO' command handler elapsed time: 19 seconds
dismissDialog("Open Synthesized Design"); // bs (cj)
// Elapsed time: 81 seconds
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
collapseTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Implementation]", 8); // ah (O, cj)
// Elapsed time: 11 seconds
expandTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, synth_1, [Vivado 12-508] No pins matched 'clkgen/inst/mmcm_adv_inst/CLKOUT0'. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc:1]. ]", 6); // ah (O, cj)
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, synth_1, [Vivado 12-508] No pins matched 'clkgen/inst/mmcm_adv_inst/CLKOUT0'. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc:1]. ]", 6, true); // ah (O, cj) - Node
messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc;-;;-;16;-;line;-;1;-;;-;16;-;"); // ah (O, cj)
// Elapsed time: 24 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design, Edit Timing Constraints]", 17, false); // u (O, cj)
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Project Manager]", 0); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Inputs (1), Set Input Delay (1)]", 12, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "4 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 5.0 ; [get_ports uart_rx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
selectButton(PAResourceEtoH.EditIODelayTablePanel_SPECIFY_CLOCK_PIN_OR_PORT, (String) null); // q (g, cj)
// p (cj): Specify Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
// Tcl Command: 'get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]'
selectList(RDIResource.HDualList_FIND_RESULTS, "clkfbout_clk_gen", 1); // f (c, p)
selectList(RDIResource.HDualList_SELECTED_NAMES, "clk_out1_clk_gen", 0); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_LEFT, "moveLeft"); // k (e, p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1); // f (c, p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clkfbout_clk_gen", 2, false, true, false, false, false); // f (c, p) - Control Key
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1, true, false, false, false, false); // f (c, p) - Shift Key
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
// Tcl Command: 'get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]'
// Elapsed time: 16 seconds
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
editTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "[get_clocks [list  [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]]", 0, "   Clock   ", 1); // v (O, cj)
dismissDialog("Specify Clock"); // p (cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Outputs (1), Set Output Delay (1)]", 14, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "5 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 1.0 ; [get_ports uart_tx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "5 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 1.0 ; [get_ports uart_tx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1, false, false, false, false, true); // v (O, cj) - Double Click
// bK (cj): Edit Set Output Delay: addNotify
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT_TO_WHICH_OUTPUT, (String) null); // q (g, bK)
// p (cj): Specify Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_out1_clk_gen", 1); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
// Tcl Command: 'get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]'
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
dismissDialog("Specify Clock"); // p (cj)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bK)
// bs (bK):  Validate XDC Command : addNotify
// [GUI Memory]: 167 MB (+2393kb) [00:51:58]
dismissDialog("Validate XDC Command"); // bs (bK)
dismissDialog("Edit Set Output Delay"); // bK (cj)
selectButton(PAResourceTtoZ.XdcEditorView_APPLY_ALL_CHANGES_TO_XDC_CONSTRAINTS, "Apply"); // a (a, cj)
// bs (cj):  Apply All XDC Constraints : addNotify
// TclEventType: SDC_CONSTR_MGR_CLEAR
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
dismissDialog("Apply All XDC Constraints"); // bs (cj)
selectButton(PAResourceCommand.PACommandNames_SAVE_DESIGN, "save_design"); // B (f, cj)
// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
// bs (cj):  Save Constraints : addNotify
// TclEventType: DESIGN_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DESIGN_SAVE
// Tcl Message: save_constraints 
dismissDialog("Save Constraints"); // bs (cj)
closeView(PAResourceOtoP.PAViews_TIMING_CONSTRAINTS, "Timing Constraints"); // a
// [GUI Memory]: 176 MB (+791kb) [00:52:14]
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
// x (cj): Run Synthesis: addNotify
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
// bs (cj):  Resetting Runs : addNotify
// TclEventType: RUN_MODIFY
dismissDialog("Run Synthesis"); // x (cj)
// TclEventType: RUN_RESET
// TclEventType: DESIGN_STALE
// TclEventType: RUN_RESET
// HMemoryUtils.trashcanNow. Engine heap size: 6,352 MB. GUI used memory: 156 MB. Current time: 7/30/20 10:47:21 AM MSK
// TclEventType: RUN_RESET
// TclEventType: RUN_MODIFY
// Tcl Message: reset_run synth_1 
// TclEventType: RUN_MODIFY
// bs (cj):  Starting Design Runs : addNotify
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: DESIGN_STALE
// TclEventType: RUN_LAUNCH
// TclEventType: RUN_MODIFY
// Tcl Message: launch_runs synth_1 -jobs 16 
// Tcl Message: [Thu Jul 30 10:47:22 2020] Launched synth_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log 
// 'k' command handler elapsed time: 7 seconds
dismissDialog("Starting Design Runs"); // bs (cj)
// Elapsed time: 26 seconds
selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // k (j, cj)
// TclEventType: DESIGN_STALE
// TclEventType: RUN_COMPLETED
// Elapsed time: 353 seconds
selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Synthesis, synth_1, [Vivado 12-508] No pins matched 'clkgen/inst/mmcm_adv_inst/CLKOUT0'. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc:1]. ]", 6, true); // ah (O, cj) - Node
messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc;-;;-;16;-;line;-;1;-;;-;16;-;"); // ah (O, cj)
// [GUI Memory]: 185 MB (+226kb) [01:00:28]
// Elapsed time: 149 seconds
selectCodeEditor("timings.xdc", 1047, 145); // cd (w, cj)
// Elapsed time: 24 seconds
selectTab((HResource) null, (HResource) null, "Sources", 1); // aF (Q, cj)
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module, Synthesis]", 3); // B (D, cj)
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i (N, cj)
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "IP Sources", 1); // i (N, cj)
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, axi_uartlite_module]", 1); // B (D, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen]", 3); // B (D, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis]", 5); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.xdc]", 14, false); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.xdc]", 14, false, false, false, false, false, true); // B (D, cj) - Double Click
// Elapsed time: 10 seconds
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen_ooc.xdc]", 15, false); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen_ooc.xdc]", 15, false, false, false, false, false, true); // B (D, cj) - Double Click
// [GUI Memory]: 198 MB (+4288kb) [01:02:07]
// Elapsed time: 21 seconds
selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "clk_gen.xdc", 3); // k (j, cj)
// Elapsed time: 12 seconds
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.v]", 13, false); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen, Synthesis, clk_gen.v]", 13, false, false, false, false, false, true); // B (D, cj) - Double Click
// HMemoryUtils.trashcanNow. Engine heap size: 6,389 MB. GUI used memory: 110 MB. Current time: 7/30/20 10:57:43 AM MSK
// Elapsed time: 13 seconds
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, IP, clk_gen]", 3); // B (D, cj)
selectTab((HResource) null, (HResource) null, "Device Constraints", 2); // aF (Q, cj)
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
closeView(PAResourceOtoP.PAViews_CODE, "Code"); // B
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design, Edit Timing Constraints]", 17, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
// Elapsed time: 16 seconds
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Clocks (2), Create Generated Clock (0)]", 2, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0, false, false, false, false, true); // n (O, cj) - Double Click
// Run Command: PAResourceCommand.PACommandNames_XDC_CREATE_GENERATED_CLOCK
// cF (cj): Design Modified on Disk: addNotify
selectButton(PAResourceOtoP.ProjectTab_RELOAD, "Reload"); // a (cF)
// 'f' command handler elapsed time: 3 seconds
// bs (cj):  Reloading : addNotify
dismissDialog("Design Modified on Disk"); // cF (cj)
// Tcl Message: refresh_design 
// TclEventType: DESIGN_REFRESH
// HMemoryUtils.trashcanNow. Engine heap size: 6,364 MB. GUI used memory: 102 MB. Current time: 7/30/20 10:58:40 AM MSK
// Engine heap size: 6,364 MB. GUI used memory: 103 MB. Current time: 7/30/20 10:58:40 AM MSK
// Tcl Message: INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen' INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite' 
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: POWER_CNS_STALE
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: FLOORPLAN_MODIFY
// TclEventType: DESIGN_REFRESH
// HMemoryUtils.trashcanNow. Engine heap size: 6,359 MB. GUI used memory: 77 MB. Current time: 7/30/20 10:58:42 AM MSK
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
// Device: addNotify
// DeviceView Instantiated
// Tcl Message: INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst' 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] 
// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 
// Tcl Message: refresh_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 7555.016 ; gain = 14.008 ; free physical = 57616 ; free virtual = 97572 
// RouteApi: Init Delay Mediator Swing Worker Finished
dismissDialog("Reloading"); // bs (cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Clocks (2), Create Generated Clock (0)]", 2, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // n (O, cj)
selectTable(PAResourceEtoH.EditCreateGeneratedClockTablePanel_EDIT_CREATE_GENERATED_CLOCK_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0, false, false, false, false, true); // n (O, cj) - Double Click
// Run Command: PAResourceCommand.PACommandNames_XDC_CREATE_GENERATED_CLOCK
// bh (cj): Create Generated Clock: addNotify
// Elapsed time: 10 seconds
setText(PAResourceEtoH.GeneratedClockCreationPanel_CLOCK_NAME, "clk_gen"); // X (Z, bh)
selectButton(PAResourceQtoS.SdcGetObjectsPanel_SPECIFY_MASTER_PIN, (String) null); // q (h, bh)
// p (cj): Specify Master Pin: addNotify
// Elapsed time: 13 seconds
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
// Elapsed time: 19 seconds
selectList(RDIResource.HDualList_FIND_RESULTS, "clkgen/clk_in1_p", 18); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
dismissDialog("Specify Master Pin"); // p (cj)
// Elapsed time: 13 seconds
selectButton(PAResourceQtoS.SdcGetObjectsPanel_SPECIFY_MASTER_CLOCK, (String) null); // q (g, bh)
// p (cj): Specify Master Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "CLK_IN_P", 0); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
dismissDialog("Specify Master Clock"); // p (cj)
setSpinner(PAResourceEtoH.GeneratedClockCreationPanel_OPTIONAL_DIVIDE_FREQUENCY, "2"); // c (N, bh)
selectButton(PAResourceQtoS.SdcGetObjectsPanel_SPECIFY_GENERATED_CLOCK_SOURCE_OBJECTS, (String) null); // q (h, bh)
// p (cj): Specify Generated Clock Source Objects: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clkgen/clk_out1", 19); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(PAResourceEtoH.GetObjectsPanel_SET, "Set"); // a (p)
dismissDialog("Specify Generated Clock Source Objects"); // p (cj)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bh)
// bs (bh):  Validate XDC Command : addNotify
// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Vivado 12-672] Cannot specify -master_clock without specifying -add.  
// CommandFailedException: null
// Tcl Message: ERROR: [Vivado 12-672] Cannot specify -master_clock without specifying -add. 
// e (cj): Validate XDC Command: addNotify
// Elapsed time: 16 seconds
selectButton(PAResourceAtoD.CmdMsgTreeDialog_OK, "OK"); // a (e)
dismissDialog("Validate XDC Command"); // e (cj)
// Elapsed time: 10 seconds
selectCheckBox(PAResourceEtoH.GeneratedClockCreationPanel_DO_NOT_OVERRIDE_CLOCKS_ALREADY_DEFINED, "Do not override clocks already defined on the same Source objects (-add)", true); // g (Z, bh): TRUE
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bh)
// bs (bh):  Validate XDC Command : addNotify
// bs (cj):  Apply XDC Constraints : addNotify
// TclEventType: SDC_CONSTRAINT_ADD
// Tcl Message: create_generated_clock -name clk_gen -source [get_pins clkgen/clk_in1_p] -divide_by 2 -add -master_clock [get_clocks CLK_IN_P] [get_pins clkgen/clk_out1] 
// 'f' command handler elapsed time: 148 seconds
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
dismissDialog("Apply XDC Constraints"); // bs (cj)
// Elapsed time: 16 seconds
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (6), Inputs (1), Set Input Delay (1)]", 12, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "4 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 5.0 ; [get_ports uart_rx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "4 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 5.0 ; [get_ports uart_rx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1, false, false, false, false, true); // v (O, cj) - Double Click
// bE (cj): Edit Set Input Delay: addNotify
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT, (String) null); // q (g, bE)
// p (cj): Specify Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
dismissDialog("Specify Clock"); // p (cj)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bE)
// bs (bE):  Validate XDC Command : addNotify
dismissDialog("Validate XDC Command"); // bs (bE)
dismissDialog("Edit Set Input Delay"); // bE (cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (6), Outputs (1), Set Output Delay (1)]", 14, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "5 ; [get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]] ; rise ;  ;  ; false ; None ; 1.0 ; [get_ports uart_tx] ; /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc ;  ; ", 0, "[get_clocks [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]", 1); // v (O, cj)
selectButton(PAResourceEtoH.EditIODelayTablePanel_SPECIFY_CLOCK_PIN_OR_PORT_TO_WHICH_OUTPUT, (String) null); // q (g, cj)
// p (cj): Specify Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
editTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, "[get_clocks clk_gen]", 0, "   Clock   ", 1); // v (O, cj)
dismissDialog("Specify Clock"); // p (cj)
selectButton(PAResourceTtoZ.XdcEditorView_APPLY_ALL_CHANGES_TO_XDC_CONSTRAINTS, "Apply"); // a (a, cj)
// bs (cj):  Apply All XDC Constraints : addNotify
// TclEventType: SDC_CONSTR_MGR_CLEAR
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-2] Deriving generated clocks 
// Tcl Message: INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. 
// Tcl Message: ERROR: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks clk_gen]'. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. 
// Tcl Message: INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. 
// Tcl Message: ERROR: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks clk_gen]'. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. 
// TclEventType: SDC_CONSTRAINT_ADD
// cg (cj): Apply All XDC Constraints: addNotify
selectButton(PAResourceAtoD.CmdMsgTreeDialog_OK, "OK"); // a (cg)
dismissDialog("Apply All XDC Constraints"); // cg (cj)
selectButton(PAResourceCommand.PACommandNames_SAVE_DESIGN, "save_design"); // B (f, cj)
// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
// bs (cj):  Save Constraints : addNotify
// TclEventType: DESIGN_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DESIGN_SAVE
// Tcl Message: save_constraints 
dismissDialog("Save Constraints"); // bs (cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (4), Inputs (0), Set Input Delay (0)]", 12, false); // bh (O, cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (4), Inputs (0), Set Input Delay (0)]", 12, false); // bh (O, cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (4), Inputs (0), Set Input Delay (0)]", 12, false, false, false, false, false, true); // bh (O, cj) - Double Click
// Run Command: PAResourceCommand.PACommandNames_XDC_SET_INPUT_DELAY
// bY (cj): Set Input Delay: addNotify
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT, (String) null); // q (g, bY)
// p (cj): Specify Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
dismissDialog("Specify Clock"); // p (cj)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bY)
// bs (bY):  Validate XDC Command : addNotify
// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-163] Missing value for option 'objects', please type 'set_input_delay -help' for usage info.  
// CommandFailedException: null
// Tcl Message: ERROR: [Common 17-163] Missing value for option 'objects', please type 'set_input_delay -help' for usage info. 
// e (cj): Validate XDC Command: addNotify
selectButton(PAResourceAtoD.CmdMsgTreeDialog_OK, "OK"); // a (e)
dismissDialog("Validate XDC Command"); // e (cj)
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_LIST_OF_PORTS, (String) null); // q (h, bY)
// p (cj): Specify Delay Objects: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "uart_rx", 3); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(PAResourceEtoH.GetObjectsPanel_SET, "Set"); // a (p)
dismissDialog("Specify Delay Objects"); // p (cj)
setSpinner(PAResourceItoN.IODelayCreationPanel_DELAY_VALUE, "1.0"); // a (ay, bY)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (bY)
// bs (bY):  Validate XDC Command : addNotify
// bs (cj):  Apply XDC Constraints : addNotify
// TclEventType: SDC_CONSTRAINT_ADD
// Tcl Message: set_input_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_rx] 
// 'u' command handler elapsed time: 32 seconds
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
dismissDialog("Apply XDC Constraints"); // bs (cj)
selectTree(PAResourceTtoZ.XdcCategoryTree_XDC_CATEGORY_TREE, "[All Categories (5), Outputs (0), Set Output Delay (0)]", 14, false); // bh (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0); // v (O, cj)
selectTable(PAResourceEtoH.EditIODelayTablePanel_EDIT_IO_DELAY_TABLE, " ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ; ", 0, (String) null, 0, false, false, false, false, true); // v (O, cj) - Double Click
// Run Command: PAResourceCommand.PACommandNames_XDC_SET_OUTPUT_DELAY
// ce (cj): Set Output Delay: addNotify
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_CLOCK_PIN_OR_PORT_TO_WHICH_OUTPUT, (String) null); // q (g, ce)
// p (cj): Specify Clock: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "clk_gen", 0); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (p)
dismissDialog("Specify Clock"); // p (cj)
selectButton(PAResourceItoN.IODelayCreationPanel_SPECIFY_LIST_OF_PORTS, (String) null); // q (h, ce)
// p (cj): Specify Delay Objects: addNotify
selectButton(PAResourceEtoH.GetObjectsDialog_FIND, "Find"); // a (i, p)
// bs (p):  Find Names : addNotify
dismissDialog("Find Names"); // bs (p)
selectList(RDIResource.HDualList_FIND_RESULTS, "uart_tx", 3); // f (c, p)
selectButton(RDIResource.HDualList_MOVE_SELECTED_ITEMS_TO_RIGHT, "moveRight"); // k (e, p)
selectButton(PAResourceEtoH.GetObjectsPanel_SET, "Set"); // a (p)
dismissDialog("Specify Delay Objects"); // p (cj)
setSpinner(PAResourceItoN.IODelayCreationPanel_DELAY_VALUE, "1.0"); // a (aW, ce)
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (ce)
// bs (ce):  Validate XDC Command : addNotify
// bs (cj):  Apply XDC Constraints : addNotify
// TclEventType: SDC_CONSTRAINT_ADD
// Tcl Message: set_output_delay -clock [get_clocks clk_gen] 1.0 [get_ports uart_tx] 
// 'A' command handler elapsed time: 22 seconds
// Run Command: PAResourceCommand.PACommandNames_TIMING_CONSTRAINTS_WINDOW
dismissDialog("Apply XDC Constraints"); // bs (cj)
selectButton(PAResourceCommand.PACommandNames_SAVE_DESIGN, "save_design"); // B (f, cj)
// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
// bs (cj):  Save Constraints : addNotify
// TclEventType: DESIGN_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DESIGN_SAVE
// Tcl Message: save_constraints 
dismissDialog("Save Constraints"); // bs (cj)
// Elapsed time: 11 seconds
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15); // u (O, cj)
closeView(PAResourceOtoP.PAViews_TIMING_CONSTRAINTS, "Timing Constraints"); // a
// Device view-level: 0.0
closeView(PAResourceOtoP.PAViews_DEVICE, "Device"); // Y
// [GUI Memory]: 210 MB (+2480kb) [01:09:07]
selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i (N, cj)
collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 4); // B (D, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints]", 3); // B (D, cj)
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1]", 4); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, timings.xdc]", 6, false); // B (D, cj)
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, timings.xdc]", 6, false, false, false, false, false, true); // B (D, cj) - Double Click
// Elapsed time: 12 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // u (O, cj)
expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Project Manager]", 0); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
// bs (cj):  Resetting Runs : addNotify
// TclEventType: RUN_MODIFY
// TclEventType: RUN_RESET
// TclEventType: DESIGN_STALE
// TclEventType: RUN_RESET
// TclEventType: RUN_MODIFY
// Tcl Message: reset_run synth_1 
// bs (cj):  Starting Design Runs : addNotify
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: DESIGN_STALE
// TclEventType: RUN_LAUNCH
// TclEventType: RUN_MODIFY
// Tcl Message: launch_runs synth_1 -jobs 16 
// Tcl Message: [Thu Jul 30 11:04:30 2020] Launched synth_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log 
dismissDialog("Starting Design Runs"); // bs (cj)
// TclEventType: DESIGN_STALE
// TclEventType: RUN_COMPLETED
// Elapsed time: 257 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aB, cj)
closeTask("Synthesis", "Synthesized Design", "DesignTask.NETLIST_PLANNING");
// x (cj): Confirm Close: addNotify
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
// TclEventType: DESIGN_CLOSE
// HMemoryUtils.trashcanNow. Engine heap size: 6,359 MB. GUI used memory: 125 MB. Current time: 7/30/20 11:08:58 AM MSK
// Engine heap size: 6,359 MB. GUI used memory: 126 MB. Current time: 7/30/20 11:08:58 AM MSK
// TclEventType: CURR_DESIGN_SET
// TclEventType: DESIGN_CLOSE
// Tcl Message: close_design 
dismissDialog("Confirm Close"); // x (cj)
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u (O, cj) - Node
// Run Command: PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN
// bs (cj):  Open Synthesized Design : addNotify
// Tcl Message: open_run synth_1 -name synth_1 
// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7k325tffg900-2 
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: POWER_CNS_STALE
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: FLOORPLAN_MODIFY
// TclEventType: DESIGN_NEW
// HMemoryUtils.trashcanNow. Engine heap size: 6,359 MB. GUI used memory: 99 MB. Current time: 7/30/20 11:09:05 AM MSK
// TclEventType: DESIGN_NEW
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
// Device: addNotify
// DeviceView Instantiated
// TclEventType: CURR_DESIGN_SET
// Tcl Message: INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen' INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite' INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst' Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst' 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] 
// Tcl Message: INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
// Device view-level: 0.0
// RouteApi: Init Delay Mediator Swing Worker Finished
// 'dO' command handler elapsed time: 5 seconds
dismissDialog("Open Synthesized Design"); // bs (cj)
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
// Elapsed time: 17 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Run Implementation]", 29, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
// bs (cj):  Starting Design Runs : addNotify
// TclEventType: FILESET_TARGET_UCF_CHANGE
// Tcl Message: launch_runs impl_1 -jobs 16 
// Tcl Message: Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. 
// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 7560.020 ; gain = 0.000 ; free physical = 57675 ; free virtual = 97641 
// TclEventType: RUN_LAUNCH
// TclEventType: RUN_MODIFY
// Tcl Message: [Thu Jul 30 11:09:28 2020] Launched impl_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log 
dismissDialog("Starting Design Runs"); // bs (cj)
// TclEventType: RUN_STEP_COMPLETED
// TclEventType: RUN_COMPLETED
// Elapsed time: 248 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 30, true); // u (O, cj) - Node
// Run Command: PAResourceCommand.PACommandNames_GOTO_IMPLEMENTED_DESIGN
// e (cj): Close Design: addNotify
selectButton(PAResourceAtoD.ClosePlanner_YES, "Yes"); // a (e)
// TclEventType: DESIGN_CLOSE
// HMemoryUtils.trashcanNow. Engine heap size: 6,374 MB. GUI used memory: 127 MB. Current time: 7/30/20 11:13:43 AM MSK
// Engine heap size: 6,374 MB. GUI used memory: 128 MB. Current time: 7/30/20 11:13:43 AM MSK
// TclEventType: CURR_DESIGN_SET
// TclEventType: DESIGN_CLOSE
// bs (cj):  Open Implemented Design : addNotify
// Tcl Message: close_design 
dismissDialog("Close Design"); // e (cj)
// Tcl Message: open_run impl_1 
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: POWER_CNS_STALE
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: DESIGN_NEW
// HMemoryUtils.trashcanNow. Engine heap size: 6,369 MB. GUI used memory: 101 MB. Current time: 7/30/20 11:13:46 AM MSK
// TclEventType: DESIGN_NEW
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
// Device: addNotify
// DeviceView Instantiated
// TclEventType: CURR_DESIGN_SET
// Tcl Message: INFO: [Netlist 29-17] Analyzing 912 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_board.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_board.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_early.xdc] 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] 
// Tcl Message: Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap_early.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp15/aes128_ecb_fpga_wrap.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. 
// Tcl Message: Read XDEF File: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 7560.020 ; gain = 0.000 ; free physical = 57677 ; free virtual = 97659 
// Tcl Message: Restored from archive | CPU: 0.250000 secs | Memory: 4.245201 MB | 
// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.25 . Memory (MB): peak = 7560.020 ; gain = 0.000 ; free physical = 57677 ; free virtual = 97659 
// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
// TclEventType: DRC_ADDED
// Device view-level: 0.0
// RouteApi: Init Delay Mediator Swing Worker Finished
// TclEventType: DRC_ADDED
// TclEventType: METHODOLOGY_ADDED
// TclEventType: POWER_UPDATED
// TclEventType: TIMING_SUMMARY_UPDATED
// 'dO' command handler elapsed time: 13 seconds
dismissDialog("Open Implemented Design"); // bs (cj)
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 33, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
// aF (cj): Report Timing Summary: addNotify
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (aF)
dismissDialog("Report Timing Summary"); // aF (cj)
// bs (cj):  Report Timing Summary : addNotify
// TclEventType: TIMING_RESULTS_STALE
// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 
// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs 
// TclEventType: TIMING_SUMMARY_UPDATED
dismissDialog("Report Timing Summary"); // bs (cj)
// Elapsed time: 21 seconds
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 5); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Check Timing]", 4); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 20); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Setup 3.098 ns]", 20, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Hold 0.094 ns]", 21, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen, Pulse Width 8.592 ns]", 24, false); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clkfbout_clk_gen]", 25); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Setup 3.098 ns]", 20, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Hold 0.094 ns]", 21, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19, true); // a (O, cj) - Node
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 17, true); // a (O, cj) - Node
selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aF (Q, cj)
// Tcl Command: 'rdi::info_commands {w*}'
// Tcl Command: 'rdi::info_commands {wr*}'
// Tcl Command: 'rdi::info_commands {wri*}'
// Tcl Command: 'rdi::info_commands {write*}'
// Tcl Command: 'rdi::info_commands {write_*}'
// Tcl Command: 'rdi::info_commands {write_v*}'
// Elapsed time: 11 seconds
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_v", true); // aF (ae, cj)
// Tcl Command: 'rdi::match_options {write_verilog} {}'
// Tcl Command: 'rdi::match_options {write_verilog} {fo}'
// Tcl Command: 'rdi::match_options {write_verilog} {for}'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -for", true); // aF (ae, cj)
// Tcl Command: 'rdi::match_options {write_verilog} {}'
// Tcl Command: 'rdi::match_options {write_verilog} {m}'
// Tcl Command: 'rdi::match_options {write_verilog} {mo}'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mo", true); // aF (ae, cj)
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./net", true); // aF (ae, cj)
// Tcl Command: 'rdi::info_commands bd::match_path'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/", true); // aF (ae, cj)
applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v"); // aF (ae, cj)
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
// Tcl Message: write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.v 
// HMemoryUtils.trashcanNow. Engine heap size: 6,376 MB. GUI used memory: 158 MB. Current time: 7/30/20 11:15:32 AM MSK
// Tcl Command: 'rdi::info_commands {write_*}'
// Tcl Command: 'rdi::info_commands {write_*}'
// Tcl Command: 'rdi::info_commands {write_s*}'
// Tcl Command: 'rdi::info_commands {write_sd*}'
// Elapsed time: 16 seconds
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sd -force -mode timesim ./netlist/aes128_ecb_wrap.v", true); // aF (ae, cj)
// Tcl Command: 'rdi::info_commands bd::match_path'
// Tcl Command: 'rdi::info_commands bd::match_path'
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.s", true); // aF (ae, cj)
applyEnter(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf"); // aF (ae, cj)
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
// Tcl Message: write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf 
// bs (cj):  Tcl Command Line : addNotify
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.sdf 
dismissDialog("Tcl Command Line"); // bs (cj)
// TclEventType: DG_GRAPH_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DG_ANALYSIS_MSG_RESET
// TclEventType: DG_GRAPH_GENERATED
// TclEventType: DG_GRAPH_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DG_ANALYSIS_MSG_RESET
// TclEventType: DG_GRAPH_GENERATED
// TclEventType: DG_GRAPH_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DG_ANALYSIS_MSG_RESET
// TclEventType: DG_GRAPH_GENERATED
// TclEventType: DG_GRAPH_STALE
// TclEventType: FILE_SET_CHANGE
// TclEventType: DG_ANALYSIS_MSG_RESET
// HMemoryUtils.trashcanNow. Engine heap size: 6,431 MB. GUI used memory: 156 MB. Current time: 7/30/20 11:42:59 AM MSK
// TclEventType: DG_GRAPH_GENERATED
// Elapsed time: 1836 seconds
selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k (aB, cj)
closeTask("Implementation", "Implemented Design", "DesignTask.RESULTS_ANALYSIS");
// x (cj): Confirm Close: addNotify
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
// TclEventType: DESIGN_CLOSE
// HMemoryUtils.trashcanNow. Engine heap size: 6,431 MB. GUI used memory: 130 MB. Current time: 7/30/20 11:46:39 AM MSK
// TclEventType: TIMING_RESULTS_UNLOAD
// Engine heap size: 6,431 MB. GUI used memory: 131 MB. Current time: 7/30/20 11:46:39 AM MSK
// TclEventType: CURR_DESIGN_SET
// TclEventType: DESIGN_CLOSE
// Tcl Message: close_design 
dismissDialog("Confirm Close"); // x (cj)
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Run Implementation]", 28, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
// bs (cj):  Resetting Runs : addNotify
// TclEventType: RUN_MODIFY
// TclEventType: RUN_RESET
// TclEventType: RUN_MODIFY
// Tcl Message: reset_run synth_1 
// bs (cj):  Starting Design Runs : addNotify
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: RUN_LAUNCH
// TclEventType: FILESET_TARGET_UCF_CHANGE
// TclEventType: RUN_LAUNCH
// TclEventType: RUN_MODIFY
// Tcl Message: launch_runs impl_1 -jobs 16 
// Tcl Message: [Thu Jul 30 11:46:45 2020] Launched synth_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log [Thu Jul 30 11:46:45 2020] Launched impl_1... Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log 
dismissDialog("Starting Design Runs"); // bs (cj)
// TclEventType: RUN_COMPLETED
// TclEventType: RUN_STEP_COMPLETED
// TclEventType: RUN_COMPLETED
// Elapsed time: 407 seconds
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 29, true); // u (O, cj) - Node
// Run Command: PAResourceCommand.PACommandNames_GOTO_IMPLEMENTED_DESIGN
// bs (cj):  Open Implemented Design : addNotify
// Tcl Message: open_run impl_1 
// TclEventType: READ_XDC_FILE_START
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: READ_XDC_FILE_END
// TclEventType: READ_XDC_FILE_START
// TclEventType: POWER_CNS_STALE
// TclEventType: POWER_REPORT_STALE
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: LOC_CONSTRAINT_REMOVE
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SIGNAL_MODIFY
// TclEventType: LOC_CONSTRAINT_ADD
// TclEventType: SDC_CONSTRAINT_ADD
// TclEventType: READ_XDC_FILE_END
// TclEventType: DESIGN_NEW
// HMemoryUtils.trashcanNow. Engine heap size: 6,436 MB. GUI used memory: 104 MB. Current time: 7/30/20 11:53:37 AM MSK
// TclEventType: DESIGN_NEW
// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
// Device: addNotify
// DeviceView Instantiated
// TclEventType: CURR_DESIGN_SET
// Tcl Message: INFO: [Netlist 29-17] Analyzing 920 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Project 1-570] Preparing netlist for logic optimization 
// Tcl Message: Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_board.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_board.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_early.xdc] 
// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57] 
// Tcl Message: Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap_early.xdc] Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap.xdc] Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-28010-gigant.modulew.local/dcp18/aes128_ecb_fpga_wrap.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. 
// Tcl Message: Read XDEF File: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 7605.039 ; gain = 0.000 ; free physical = 57798 ; free virtual = 97758 
// Tcl Message: Restored from archive | CPU: 0.260000 secs | Memory: 4.378311 MB | 
// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.26 . Memory (MB): peak = 7605.039 ; gain = 0.000 ; free physical = 57798 ; free virtual = 97758 
// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
// Device view-level: 0.0
// TclEventType: DRC_ADDED
// RouteApi: Init Delay Mediator Swing Worker Finished
// TclEventType: DRC_ADDED
// TclEventType: METHODOLOGY_ADDED
// TclEventType: POWER_UPDATED
// TclEventType: TIMING_SUMMARY_UPDATED
// 'dO' command handler elapsed time: 7 seconds
dismissDialog("Open Implemented Design"); // bs (cj)
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 33, false); // u (O, cj)
// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
// aF (cj): Report Timing Summary: addNotify
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (aF)
// [GUI Memory]: 222 MB (+1711kb) [01:58:50]
dismissDialog("Report Timing Summary"); // aF (cj)
// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 
// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs 
// TclEventType: TIMING_RESULTS_STALE
// bs (cj):  Report Timing Summary : addNotify
// TclEventType: TIMING_SUMMARY_UPDATED
dismissDialog("Report Timing Summary"); // bs (cj)
// [GUI Memory]: 238 MB (+4100kb) [01:59:00]
// Elapsed time: 10 seconds
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Check Timing]", 4); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths]", 17); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Setup 2.583 ns]", 20, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Hold 0.085 ns]", 21, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen, Pulse Width 4.358 ns]", 22, false); // a (O, cj)
selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_gen]", 19, true); // a (O, cj) - Node
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clk_out1_clk_gen]", 23); // a (O, cj)
expandTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Intra-Clock Paths, clkfbout_clk_gen]", 25); // a (O, cj)
selectTab((HResource) null, (HResource) null, "Tcl Console", 0); // aF (Q, cj)
// Elapsed time: 13 seconds
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v", true); // aF (ae, cj)
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
// Tcl Command: 'write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v'
// Tcl Message: write_verilog -force -mode timesim ./netlist/aes128_ecb_wrap.v 
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.v 
// HMemoryUtils.trashcanNow. Engine heap size: 6,456 MB. GUI used memory: 160 MB. Current time: 7/30/20 11:54:46 AM MSK
// Elapsed time: 16 seconds
setText(RDIResource.CommandsInput_TYPE_TCL_COMMAND_HERE, "write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf", true); // aF (ae, cj)
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
// Tcl Command: 'write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf'
// Tcl Message: write_sdf -force -mode timesim ./netlist/aes128_ecb_wrap.sdf 
// bs (cj):  Tcl Command Line : addNotify
// Tcl Message: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb_2017/netlist/aes128_ecb_wrap.sdf 
dismissDialog("Tcl Command Line"); // bs (cj)