Subversion Repositories ahbmaster

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>top_CoreAHBLite_0_CoreAHBLite</name><vendor/><library/><version/><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>coreparameters.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="1"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="2"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="3"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="4"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="5"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="6"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="7"><name>..\..\..\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="8"><name>rtl\vhdl\test\user\testbench.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="9"><name>rtl\vhdl\core\components.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="10"><name>rtl\vhdl\core\coreahblite.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>