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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [designer/] [impl1/] [designer_synth_check.log] - Rev 3

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Microsemi Libero Software
Version: 11.8.3.6
Release: v11.8 SP3

Created a new design.
'BA_NAME' set to 'top_ba'
'IDE_DESIGNERVIEW_NAME' set to 'Impl1'
'IDE_DESIGNERVIEW_COUNT' set to '1'
'IDE_DESIGNERVIEW_REV0' set to 'Impl1'
'IDE_DESIGNERVIEW_REVNUM0' set to '1'
'IDE_DESIGNERVIEW_ROOTDIR' set to 'C:\Actelprj\test79_AHBmaster\designer'
'IDE_DESIGNERVIEW_LASTREV' set to '1'
'DESDIR' set to 'C:/Actelprj/test79_AHBmaster/designer/impl1'
'BA_DIR' set to 'C:/Actelprj/test79_AHBmaster/designer/impl1'
'BA_NETLIST_ALSO' set to '1'
'EDNINFLAVOR' set to 'GENERIC'
'NETLIST_NAMING_STYLE' set to 'VHDL93'
'EXPORT_STATUS_REPORT' set to '1'
'EXPORT_STATUS_REPORT_FILENAME' set to 'top.rpt'
'AUDIT_NETLIST_FILE' set to '1'
'AUDIT_DCF_FILE' set to '1'
'AUDIT_PIN_FILE' set to '1'
'AUDIT_ADL_FILE' set to '1'

 Netlist Reading Time = 0.0 seconds
Imported the file:
   C:\Actelprj\test79_AHBmaster\synthesis\top.edn

The Import command succeeded ( 00:00:03 )
Wrote to the file: ..\..\synthesis\top.vhd

The Export command succeeded ( 00:00:02 )

The Execute Script command succeeded ( 00:00:11 )
Warning: The database was closed without a save, modifications are lost
Design closed.

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