Subversion Repositories ahbmaster

#--  Synopsys, Inc.
#--  Version L-2016.09M-2
#--  Project file C:\Actelprj\test79_AHBmaster\synthesis\scratchproject.prs

#project files
add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/hdl/AHBMASTER_FIC.vhd"
add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHB2APB/1.1.101/rtl/vhdl/u/CoreAHB2APB.vhd"
add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAPB/1.1.101/rtl/vhdl/o/MuxP2B.vhd"
add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAPB/1.1.101/rtl/vhdl/o/CoreAPB.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_addrdec.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_defaultslavesm.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_masterstage.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_slavearbiter.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_slavestage.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_matrix4x16.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_pkg.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreAHBLite_0/rtl/vhdl/core/coreahblite.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/Clock_gen.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/Rx_async.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/Tx_async.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/fifo_256x8_pa3.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/coreuart_pkg.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/CoreUART.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/CoreUARTapb.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreAHBLite_0/rtl/vhdl/core/components.vhd"
add_file -vhdl -lib COREUARTAPB_LIB "C:/Actelprj/test79_AHBmaster/component/work/top/CoreUARTapb_0/rtl/vhdl/core/components.vhd"
add_file -vhdl -lib work "C:/Actelprj/test79_AHBmaster/component/work/top/top.vhd"



#implementation: "synthesis"
impl -add C:\Actelprj\test79_AHBmaster\synthesis -type fpga

#device options
set_option -technology ProASIC3
set_option -part A3PN250
set_option -package VQFP100
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.top"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microsemi 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Microsemi 500K
set_option -globalthreshold 50

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

# Compiler Options
set_option -vhdl2008 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "C:/Actelprj/test79_AHBmaster/synthesis/top.edn"
impl -active "synthesis"