Subversion Repositories ahbmaster

@W: CD638 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Signal controlreg3 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":265:21:265:31|Signal rx_dout_reg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":265:34:265:49|Signal parity_err_xhdl1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd":443:6:443:7|Sharing sequential element clear_framing_error_en_i. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd":134:4:134:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
@W: CD638 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd":54:7:54:19|Signal baud_cntr_one is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":439:7:439:8|Pruning unused register overflow_reg_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":414:7:414:8|Pruning unused register rx_dout_reg_empty_5. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":399:6:399:7|Pruning unused register rx_dout_reg_5(7 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":367:6:367:7|Pruning unused register rx_state_4(1 downto 0). Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":350:6:350:7|Pruning unused register clear_framing_error_reg0_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":350:6:350:7|Pruning unused register clear_framing_error_reg_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":333:6:333:7|Pruning unused register clear_parity_reg0_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":333:6:333:7|Pruning unused register clear_parity_reg_3. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd":245:6:245:7|Pruning unused register fifo_write_tx_4. Make sure that there are no unused intermediate registers.
@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 0 of signal controlReg3 is floating -- simulation mismatch possible.
@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 1 of signal controlReg3 is floating -- simulation mismatch possible.
@W: CL252 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":153:10:153:20|Bit 2 of signal controlReg3 is floating -- simulation mismatch possible.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":339:8:339:17|Signal sdataready in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":340:8:340:13|Signal shresp in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":341:8:341:16|Signal hrdata_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":341:20:341:31|Signal hreadyout_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:8:342:16|Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:20:342:31|Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:8:343:16|Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:20:343:31|Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:8:344:16|Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:20:344:31|Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:16|Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:20:345:31|Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:8:346:16|Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:20:346:31|Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:8:347:16|Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:20:347:31|Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:8:348:16|Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:20:348:31|Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:8:349:16|Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:20:349:31|Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:8:350:16|Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:20:350:31|Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:8:351:17|Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:20:351:32|Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:8:352:17|Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:20:352:32|Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:8:353:17|Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:20:353:32|Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:8:354:17|Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:20:354:32|Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:8:355:17|Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:20:355:32|Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:17|Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:20:356:32|Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:8:357:17|Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:20:357:32|Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:8:342:16|Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":342:20:342:31|Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:8:343:16|Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":343:20:343:31|Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:8:344:16|Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":344:20:344:31|Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:8:345:16|Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":345:20:345:31|Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:8:346:16|Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":346:20:346:31|Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:8:347:16|Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":347:20:347:31|Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:8:348:16|Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":348:20:348:31|Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:8:349:16|Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":349:20:349:31|Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:8:350:16|Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":350:20:350:31|Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:8:351:17|Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":351:20:351:32|Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:8:352:17|Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":352:20:352:32|Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:8:353:17|Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":353:20:353:32|Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:8:354:17|Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":354:20:354:32|Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:8:355:17|Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":355:20:355:32|Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:8:356:17|Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":356:20:356:32|Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:8:357:17|Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":357:20:357:32|Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CL177 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":644:8:644:9|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CD274 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":118:3:118:6|Incomplete case statement - add more cases or a when others
@W: CL190 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd":20:4:20:9|Input port bit 0 of htrans(1 downto 0) is unused 
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":45:8:45:17|Input port bits 16 to 1 of sdataready(16 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd":46:8:46:13|Input port bits 16 to 1 of shresp(16 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":124:0:124:8|Input port bit 0 of htrans_m0(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":135:0:135:8|Input port bit 0 of htrans_m1(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":146:0:146:8|Input port bit 0 of htrans_m2(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":157:0:157:8|Input port bit 0 of htrans_m3(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":167:0:167:7|Input port bit 1 of hresp_s0(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":180:0:180:7|Input port bit 1 of hresp_s1(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":193:0:193:7|Input port bit 1 of hresp_s2(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":206:0:206:7|Input port bit 1 of hresp_s3(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":219:0:219:7|Input port bit 1 of hresp_s4(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":232:0:232:7|Input port bit 1 of hresp_s5(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":245:0:245:7|Input port bit 1 of hresp_s6(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":258:0:258:7|Input port bit 1 of hresp_s7(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":271:0:271:7|Input port bit 1 of hresp_s8(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":284:0:284:7|Input port bit 1 of hresp_s9(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":297:0:297:8|Input port bit 1 of hresp_s10(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":310:0:310:8|Input port bit 1 of hresp_s11(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":323:0:323:8|Input port bit 1 of hresp_s12(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":336:0:336:8|Input port bit 1 of hresp_s13(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":349:0:349:8|Input port bit 1 of hresp_s14(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":362:0:362:8|Input port bit 1 of hresp_s15(1 downto 0) is unused 
@W: CL247 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd":375:0:375:8|Input port bit 1 of hresp_s16(1 downto 0) is unused 
@W: CL246 :"C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd":83:6:83:10|Input port bits 1 to 0 of paddr(4 downto 0) are unused. Assign logic for all port bits or change the input port size.