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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synplify.log] - Rev 3

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Starting:    C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin64\mbin\synbatch.exe
Install:     C:\Microsemi\Libero_SoC_v11.8\SynplifyPro
Hostname:    H81I
Date:        Sat Jun 02 22:53:08 2018
Version:     L-2016.09M-2

Arguments:   -product synplify_pro -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro

License checkout: synplifypro_actel
License: synplifypro_actel node-locked 
Licensed Vendor: actel
License Option: actel_oem

Running in Vendor Mode


Implementation not found: synthesis

log file: "C:\Actelprj\test79_AHBmaster\synthesis\top.srr"

Running: synthesis in foreground



Running top_syn|synthesis


Running: compile (Compile) on top_syn|synthesis
# Sat Jun 02 22:53:08 2018


Running: compile_flow (Compile Process) on top_syn|synthesis
# Sat Jun 02 22:53:08 2018


Running: compiler (Compile Input) on top_syn|synthesis
# Sat Jun 02 22:53:08 2018

Copied C:\Actelprj\test79_AHBmaster\synthesis\synwork\top_comp.srs to C:\Actelprj\test79_AHBmaster\synthesis\top.srs


compiler completed
# Sat Jun 02 22:53:13 2018

Return Code: 0
Run Time:00h:00m:05s


Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Sat Jun 02 22:53:13 2018


multi_srs_gen completed
# Sat Jun 02 22:53:13 2018

Return Code: 0
Run Time:00h:00m:00s

Copied C:\Actelprj\test79_AHBmaster\synthesis\synwork\top_mult.srs to C:\Actelprj\test79_AHBmaster\synthesis\top.srs

Complete: Compile Process on top_syn|synthesis


Running: premap (Pre-mapping) on top_syn|synthesis
# Sat Jun 02 22:53:13 2018


premap completed with warnings
# Sat Jun 02 22:53:14 2018

Return Code: 1
Run Time:00h:00m:01s

Complete: Compile on top_syn|synthesis


Running: map (Map) on top_syn|synthesis
# Sat Jun 02 22:53:14 2018

License granted for 4 parallel jobs


Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Sat Jun 02 22:53:14 2018

Copied C:\Actelprj\test79_AHBmaster\synthesis\synwork\top_m.srm to C:\Actelprj\test79_AHBmaster\synthesis\top.srm


fpga_mapper completed with warnings
# Sat Jun 02 22:53:21 2018

Return Code: 1
Run Time:00h:00m:07s

Complete: Map on top_syn|synthesis

Complete: Logic Synthesis on top_syn|synthesis

Copied C:\Actelprj\test79_AHBmaster\synthesis\top.srr to C:\Actelprj\test79_AHBmaster\synthesis\backup\top.srr

TCL script complete: "top_syn.tcl"

exit status=0

exit status=0

License checkin: synplifypro_actel

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