OpenCores
URL https://opencores.org/ocsvn/ahbmaster/ahbmaster/trunk

Subversion Repositories ahbmaster

[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [test79_AHBmaster.prjx] - Rev 3

Compare with Previous | Blame | View Log 

KEY LIBERO "11.8"
KEY CAPTURE "11.8.3.6"
KEY DEFAULT_IMPORT_LOC "D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_new\AHB_master_fabric\component\work\Top"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0"
KEY HDLTechnology "VHDL"
KEY VERILOGMODE "VERILOG2001"
KEY VHDLMODE "VHDL2008"
KEY UseConstraintFlowTechnology "FALSE"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "UM4X4M1N"
KEY VendorTechnology_Package "vq100"
KEY VendorTechnology_Speed "STD"
KEY VendorTechnology_DieVoltage "1.5"
KEY VendorTechnology_PART_RANGE "IND"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE ""
KEY VendorTechnology_IO_DEFT_STD "LVTTL"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY ""
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE ""
KEY VendorTechnology_TARGETDEVICESFORMIGRATION "UM4X4M1N"
KEY VendorTechnology_TEMPR "IND"
KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "IND"
KEY ProjectLocation "C:\Actelprj\test79_AHBmaster"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
COREAHBLITE_LIB
COREUARTAPB_LIB
ENDLIST
LIST LIBRARY_COREAHBLITE_LIB
ALIAS=..\component\Actel\DirectCore\CoreAHBLite\5.3.101\mti\user_vhdl\COREAHBLITE_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_COREUARTAPB_LIB
ALIAS=COREUARTAPB_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST FileManager
VALUE "<project>\component\Actel\DirectCore\CoreAHB2APB\1.1.101\CoreAHB2APB.cxf,actgen_cxf"
STATE="utd"
TIME="1527947576"
SIZE="479"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="25936"
PARENT="<project>\component\Actel\DirectCore\CoreAHB2APB\1.1.101\CoreAHB2APB.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf,actgen_cxf"
STATE="utd"
TIME="1527947577"
SIZE="4352"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\mti\scripts\wave_user.do,do"
STATE="utd"
TIME="1527947216"
SIZE="912"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="8290"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="2348"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="22169"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="82848"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="45707"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="12780"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
STATE="utd"
TIME="1527947216"
SIZE="23829"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="11215"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="2760"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="30586"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="426134"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="425"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="17249"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="12256"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB\1.1.101\CoreAPB.cxf,actgen_cxf"
STATE="utd"
TIME="1527947577"
SIZE="568"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="9093"
PARENT="<project>\component\Actel\DirectCore\CoreAPB\1.1.101\CoreAPB.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd,hdl"
STATE="utd"
TIME="1527947216"
SIZE="3954"
PARENT="<project>\component\Actel\DirectCore\CoreAPB\1.1.101\CoreAPB.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreUARTapb\5.6.102\CoreUARTapb.cxf,actgen_cxf"
STATE="utd"
TIME="1527947577"
SIZE="779"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
STATE="utd"
TIME="1527947577"
SIZE="437"
ENDFILE
VALUE "<project>\component\work\DESIGN_IO\DESIGN_IO.cxf,actgen_cxf"
STATE="utd"
TIME="1527947584"
SIZE="413"
ENDFILE
VALUE "<project>\component\work\tb_top\tb_top.cxf,actgen_cxf"
STATE="utd"
TIME="1527947563"
SIZE="2058"
ENDFILE
VALUE "<project>\component\work\tb_top\tb_top.vhd,tb_hdl"
STATE="utd"
TIME="1527947563"
SIZE="4599"
PARENT="<project>\component\work\tb_top\tb_top.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="4439"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="18847"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="62342"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="68328"
LIBRARY="COREAHBLITE_LIB"
PARENT="<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf"
MODULE_UNDER_TEST="testbench"
SIMULATION_TIME="-all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreAHBLite_0\top_CoreAHBLite_0_CoreAHBLite.cxf,actgen_cxf"
STATE="utd"
TIME="1527947577"
SIZE="2631"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="970"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\mti\scripts\bfmtovec_compile.do,do"
STATE="utd"
TIME="1527947577"
SIZE="1011"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\mti\scripts\wave_vhdl_amba.do,do"
STATE="utd"
TIME="1527947577"
SIZE="1933"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="8379"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="11124"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="2437"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="22276"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="4080"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="9647"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="2163"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="12526"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="4078"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="82918"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="45926"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="12888"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="23848"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="12888"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="2707"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="22268"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="17722"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="487"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="8434"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="21552"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="11195"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
STATE="utd"
TIME="1527947577"
SIZE="12626"
LIBRARY="COREUARTAPB_LIB"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
MODULE_UNDER_TEST="testbench"
SIMULATION_TIME="-all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf,actgen_cxf"
STATE="utd"
TIME="1527947577"
SIZE="5832"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\component\work\top\top.cxf,actgen_cxf"
STATE="utd"
TIME="1527947584"
SIZE="4888"
ENDFILE
VALUE "<project>\component\work\top\top.vhd,hdl"
STATE="utd"
TIME="1527947577"
SIZE="61971"
PARENT="<project>\component\work\top\top.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\AHBMASTER_FIC.ide_des,ide_des"
STATE="utd"
TIME="1527781363"
SIZE="193"
ENDFILE
VALUE "<project>\designer\impl1\top.ide_des,ide_des"
STATE="utd"
TIME="1527947605"
SIZE="183"
ENDFILE
VALUE "<project>\hdl\AHBMASTER_FIC.vhd,hdl"
STATE="utd"
TIME="1527947376"
SIZE="6787"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
STATE="utd"
TIME="1527947216"
SIZE="1462"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
STATE="utd"
TIME="1527947216"
SIZE="25928"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
STATE="utd"
TIME="1527947216"
SIZE="6200"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
STATE="utd"
TIME="1527947216"
SIZE="6200"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
STATE="utd"
TIME="1527947216"
SIZE="6200"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
STATE="utd"
TIME="1527947216"
SIZE="12178"
PARENT="<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\CoreAHBLite.cxf"
ENDFILE
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
STATE="utd"
TIME="1527947217"
SIZE="2906"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
STATE="utd"
TIME="1527947217"
SIZE="13597"
PARENT="<project>\component\work\top\CoreUARTapb_0\top_CoreUARTapb_0_CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1527947638"
SIZE="1831"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1527947577"
SIZE="793"
PARENT="<project>\component\work\top\top.cxf"
ENDFILE
VALUE "<project>\simulation\tb_top_postsynth_simulation.log,log"
STATE="utd"
TIME="1527947753"
SIZE="13308"
ENDFILE
VALUE "<project>\stimulus\tb_clk.vhd,tb_hdl"
STATE="utd"
TIME="1527947528"
SIZE="1316"
ENDFILE
VALUE "<project>\synthesis\AHBMASTER_FIC.edn,syn_edn"
STATE="utd"
TIME="1527947400"
SIZE="207006"
ENDFILE
VALUE "<project>\synthesis\AHBMASTER_FIC.so,so"
STATE="utd"
TIME="1527947400"
SIZE="224"
ENDFILE
VALUE "<project>\synthesis\AHBMASTER_FIC_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1527947400"
SIZE="404"
ENDFILE
VALUE "<project>\synthesis\AHBMASTER_FIC_syn.prj,prj"
STATE="utd"
TIME="1527947401"
SIZE="1660"
ENDFILE
VALUE "<project>\synthesis\synwork\layer0.so,so"
STATE="utd"
TIME="1527947243"
SIZE="159"
ENDFILE
VALUE "<project>\synthesis\top.edn,syn_edn"
STATE="utd"
TIME="1527947601"
SIZE="586319"
ENDFILE
VALUE "<project>\synthesis\top.so,so"
STATE="utd"
TIME="1527947601"
SIZE="204"
ENDFILE
VALUE "<project>\synthesis\top.vhd,syn_hdl"
STATE="utd"
TIME="1527947637"
SIZE="309167"
ENDFILE
VALUE "<project>\synthesis\top_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1527947601"
SIZE="394"
ENDFILE
VALUE "<project>\synthesis\top_syn.prj,prj"
STATE="utd"
TIME="1527947601"
SIZE="4525"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "AHBMASTER_FIC::work"
FILE "<project>\hdl\AHBMASTER_FIC.vhd,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\AHBMASTER_FIC.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "top::work"
FILE "<project>\component\work\top\top.vhd,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\stimulus\tb_clk.vhd,tb_hdl"
VALUE "<project>\component\work\tb_top\tb_top.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\top.edn,syn_edn)=StateSuccess
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components"
FILE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd,hdl"
LIST Other_Association
VALUE "<project>\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components"
FILE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd,hdl"
LIST Other_Association
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
VALUE "<project>\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\mti\scripts\bfmtovec_compile.do,do"
VALUE "<project>\component\work\top\CoreUARTapb_0\mti\scripts\wave_vhdl_amba.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST top
VALUE "<project>\stimulus\tb_clk.vhd,tb_hdl"
VALUE "<project>\component\work\tb_top\tb_top.vhd,tb_hdl"
ENDLIST
LIST top_CoreAHBLite_0_CoreAHBLite
VALUE "<project>\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
LIST top_CoreUARTapb_0_CoreUARTapb
VALUE "<project>\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST top
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST top_CoreAHBLite_0_CoreAHBLite
VALUE "<project>\component\work\top\CoreAHBLite_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
ENDLIST
LIST top_CoreUARTapb_0_CoreUARTapb
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
VALUE "<project>\component\work\top\CoreUARTapb_0\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd,tb_hdl"
VALUE "<project>\component\work\top\CoreUARTapb_0\mti\scripts\bfmtovec_compile.do,do"
VALUE "<project>\component\work\top\CoreUARTapb_0\mti\scripts\wave_vhdl_amba.do,do"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=tb_top
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
InstantiateInSmartDesign=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin\synplify_pro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_SoC_v11.8\Modelsim\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FPExpress"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_SoC_v11.8\Designer\bin\FPExpress.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="C:\Microsemi\Libero_SoC_v11.8\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "AHBMASTER_FIC::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\AHBMASTER_FIC.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "top::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\top.edn,syn_edn)=StateSuccess
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Synthesize:synplify.log
SmartDesign;top;0
HDL;hdl\AHBMASTER_FIC.vhd;0
SmartDesign;tb_top;0
StartPage;StartPage;0
ACTIVEVIEW;top
ENDLIST
LIST ModuleSubBlockList
LIST "AHBMASTER_FIC::work","hdl\AHBMASTER_FIC.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreAHB2APB::work","component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreAPB::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd","FALSE","FALSE"
SUBBLOCK "CoreAPB_L::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreAPB_L::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
ENDLIST
LIST "DESIGN_IO::work","component\work\DESIGN_IO\DESIGN_IO.cxf","TRUE","FALSE"
ENDLIST
LIST "top::work","component\work\top\top.vhd","TRUE","FALSE"
SUBBLOCK "AHBMASTER_FIC::work","hdl\AHBMASTER_FIC.vhd","FALSE","FALSE"
SUBBLOCK "CoreAHB2APB::work","component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd","FALSE","FALSE"
SUBBLOCK "CoreAPB::work","component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
ENDLIST
LIST "tb_clk::work","stimulus\tb_clk.vhd","FALSE","TRUE"
ENDLIST
LIST "tb_top::work","component\work\tb_top\tb_top.vhd","TRUE","TRUE"
SUBBLOCK "tb_clk::work","stimulus\tb_clk.vhd","FALSE","TRUE"
SUBBLOCK "top::work","component\work\top\top.vhd","TRUE","FALSE"
ENDLIST
LIST "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd","FALSE","FALSE"
ENDLIST
LIST "coreahblite_pkg::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd","FALSE","FALSE"
ENDLIST
LIST "coreahblite_support::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreAHBLite_0_components::COREAHBLITE_LIB","component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd","FALSE","FALSE"
ENDLIST
LIST "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
SUBBLOCK "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "bfM_ahblAPB::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
SUBBLOCK "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_APb::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "Bfm_aPB2apb::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "BFM_apbSLAve::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "BFm_apBSLaveEXT::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_misc::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\misc.vhd","FALSE","TRUE"
ENDLIST
LIST "bfM_packAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_package.vhd","FALSE","TRUE"
SUBBLOCK "BFMA1i1lI::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
SUBBLOCK "BFM_apbSLAve::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "BFm_apBSLaveEXT::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
SUBBLOCK "Bfm_aPB2apb::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
SUBBLOCK "bfM_ahblAPB::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "bfm_APb::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_textio::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_textio_test::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
ENDLIST
LIST "BFMA1i1lI::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "coreparameters::COREAHBLITE_LIB","component\work\top\CoreAHBLite_0\coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAHBLITE_LIB","component\work\top\CoreAHBLite_0\rtl\vhdl\test\user\testbench.vhd","FALSE","TRUE"
SUBBLOCK "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
SUBBLOCK "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreAHBLite_0_CoreAHBLite::COREAHBLITE_LIB::top_CoreAHBLite_0_components","component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_Clock_gen::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_components::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_COREUART::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_Clock_gen::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_Rx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_Tx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_fifo_256x8::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_coreuart_pkg::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_COREUART::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_fifo_256x8::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_fifo_256x8_pa3::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_fifo_256x8_pa3::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_Rx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd","FALSE","FALSE"
ENDLIST
LIST "top_CoreUARTapb_0_Tx_async::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd","FALSE","FALSE"
ENDLIST
LIST "bfm_misc::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\misc.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_textio::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
ENDLIST
LIST "bfm_textio_test::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\textio.vhd","FALSE","TRUE"
ENDLIST
LIST "coreparameters::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "testbench::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\test\user\testbench.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_CoreUARTapb::COREUARTAPB_LIB::top_CoreUARTapb_0_components","component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd","FALSE","FALSE"
SUBBLOCK "top_CoreUARTapb_0_BFM_APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_AHBL::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_AHBLAPB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_AHBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBSLAVEEXt::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_AHBSLAVEEXt::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_APB2APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_APBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_APBSLAVEEXT::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_APBSLAVEEXT::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_bfM_packAGE::COREUARTAPB_LIB","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_package.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBL::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbl.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBLAPB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahblapb.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslave.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_AHBSLAVEEXt::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apb.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_APB2APB::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbtoapb.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_APBSLAVE::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslave.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_APBSLAVEEXT::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_apbslaveext.vhd","FALSE","TRUE"
SUBBLOCK "top_CoreUARTapb_0_BFM_MAIN::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_main.vhd","FALSE","TRUE"
ENDLIST
LIST "top_CoreUARTapb_0_BFMA1i1lI::COREUARTAPB_LIB::top_CoreUARTapb_0_bfM_packAGE","component\work\top\CoreUARTapb_0\rtl\vhdl\amba_bfm\bfm_ahbtoapb.vhd","FALSE","TRUE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
LIST "top::work"
ACTIVETESTBENCH "tb_top::work","component\work\tb_top\tb_top.vhd","TRUE"
ENDLIST
LIST "AHBMASTER_FIC::work"
ACTIVETESTBENCH "tb_top::work","component\work\tb_top\tb_top.cxf","TRUE"
ENDLIST
ENDLIST
LIST IOTabList
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
ENDLIST
LIST FDCTabList
ENDLIST

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.