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Implementation;Synthesis;RootName:top
Implementation;Synthesis|| CD638 ||@W:Signal controlreg3 is undriven. Either assign the signal a value or remove the signal declaration.||top.srr(28);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/28||CoreUARTapb.vhd(153);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd'/linenumber/153
Implementation;Synthesis|| CD434 ||@W:Signal rx_dout_reg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(30);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/30||CoreUART.vhd(265);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/265
Implementation;Synthesis|| CD434 ||@W:Signal parity_err_xhdl1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(31);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/31||CoreUART.vhd(265);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/265
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element clear_framing_error_en_i. Add a syn_preserve attribute to the element to prevent sharing.||top.srr(42);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/42||Rx_async.vhd(443);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd'/linenumber/443
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(46);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/46||Tx_async.vhd(134);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd'/linenumber/134
Implementation;Synthesis|| CL169 ||@W:Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.||top.srr(47);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/47||Tx_async.vhd(134);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd'/linenumber/134
Implementation;Synthesis|| CD638 ||@W:Signal baud_cntr_one is undriven. Either assign the signal a value or remove the signal declaration.||top.srr(49);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/49||Clock_gen.vhd(54);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd'/linenumber/54
Implementation;Synthesis|| CL169 ||@W:Pruning unused register overflow_reg_3. Make sure that there are no unused intermediate registers.||top.srr(52);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/52||CoreUART.vhd(439);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/439
Implementation;Synthesis|| CL169 ||@W:Pruning unused register rx_dout_reg_empty_5. Make sure that there are no unused intermediate registers.||top.srr(53);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/53||CoreUART.vhd(414);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/414
Implementation;Synthesis|| CL169 ||@W:Pruning unused register rx_dout_reg_5(7 downto 0). Make sure that there are no unused intermediate registers.||top.srr(54);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/54||CoreUART.vhd(399);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/399
Implementation;Synthesis|| CL169 ||@W:Pruning unused register rx_state_4(1 downto 0). Make sure that there are no unused intermediate registers.||top.srr(55);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/55||CoreUART.vhd(367);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/367
Implementation;Synthesis|| CL169 ||@W:Pruning unused register clear_framing_error_reg0_3. Make sure that there are no unused intermediate registers.||top.srr(56);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/56||CoreUART.vhd(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/350
Implementation;Synthesis|| CL169 ||@W:Pruning unused register clear_framing_error_reg_3. Make sure that there are no unused intermediate registers.||top.srr(57);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/57||CoreUART.vhd(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/350
Implementation;Synthesis|| CL169 ||@W:Pruning unused register clear_parity_reg0_3. Make sure that there are no unused intermediate registers.||top.srr(58);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/58||CoreUART.vhd(333);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/333
Implementation;Synthesis|| CL169 ||@W:Pruning unused register clear_parity_reg_3. Make sure that there are no unused intermediate registers.||top.srr(59);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/59||CoreUART.vhd(333);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/333
Implementation;Synthesis|| CL169 ||@W:Pruning unused register fifo_write_tx_4. Make sure that there are no unused intermediate registers.||top.srr(60);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/60||CoreUART.vhd(245);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd'/linenumber/245
Implementation;Synthesis|| CL252 ||@W:Bit 0 of signal controlReg3 is floating -- simulation mismatch possible.||top.srr(62);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/62||CoreUARTapb.vhd(153);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd'/linenumber/153
Implementation;Synthesis|| CL252 ||@W:Bit 1 of signal controlReg3 is floating -- simulation mismatch possible.||top.srr(63);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/63||CoreUARTapb.vhd(153);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd'/linenumber/153
Implementation;Synthesis|| CL252 ||@W:Bit 2 of signal controlReg3 is floating -- simulation mismatch possible.||top.srr(64);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/64||CoreUARTapb.vhd(153);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd'/linenumber/153
Implementation;Synthesis|| CD434 ||@W:Signal sdataready in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(78);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/78||coreahblite_masterstage.vhd(339);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/339
Implementation;Synthesis|| CD434 ||@W:Signal shresp in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(79);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/79||coreahblite_masterstage.vhd(340);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/340
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(80);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/80||coreahblite_masterstage.vhd(341);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/341
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s0 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(81);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/81||coreahblite_masterstage.vhd(341);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/341
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(82);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/82||coreahblite_masterstage.vhd(342);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/342
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(83);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/83||coreahblite_masterstage.vhd(342);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/342
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(84);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/84||coreahblite_masterstage.vhd(343);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/343
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(85);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/85||coreahblite_masterstage.vhd(343);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/343
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(86);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/86||coreahblite_masterstage.vhd(344);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/344
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(87);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/87||coreahblite_masterstage.vhd(344);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/344
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(88);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/88||coreahblite_masterstage.vhd(345);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/345
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(89);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/89||coreahblite_masterstage.vhd(345);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/345
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(90);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/90||coreahblite_masterstage.vhd(346);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/346
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(91);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/91||coreahblite_masterstage.vhd(346);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/346
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(92);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/92||coreahblite_masterstage.vhd(347);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/347
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(93);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/93||coreahblite_masterstage.vhd(347);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/347
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(94);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/94||coreahblite_masterstage.vhd(348);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/348
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(95);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/95||coreahblite_masterstage.vhd(348);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/348
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(96);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/96||coreahblite_masterstage.vhd(349);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/349
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(97);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/97||coreahblite_masterstage.vhd(349);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/349
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(98);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/98||coreahblite_masterstage.vhd(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/350
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(99);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/99||coreahblite_masterstage.vhd(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/350
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(100);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/100||coreahblite_masterstage.vhd(351);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/351
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(101);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/101||coreahblite_masterstage.vhd(351);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/351
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(102);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/102||coreahblite_masterstage.vhd(352);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/352
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(103);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/103||coreahblite_masterstage.vhd(352);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/352
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(104);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/104||coreahblite_masterstage.vhd(353);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/353
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(105);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/105||coreahblite_masterstage.vhd(353);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/353
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(106);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/106||coreahblite_masterstage.vhd(354);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/354
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(107);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/107||coreahblite_masterstage.vhd(354);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/354
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(108);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/108||coreahblite_masterstage.vhd(355);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/355
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(109);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/109||coreahblite_masterstage.vhd(355);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/355
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(110);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/110||coreahblite_masterstage.vhd(356);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/356
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(111);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/111||coreahblite_masterstage.vhd(356);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/356
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(112);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/112||coreahblite_masterstage.vhd(357);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/357
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(113);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/113||coreahblite_masterstage.vhd(357);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/357
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.||top.srr(121);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/121||coreahblite_masterstage.vhd(644);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/644
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(123);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/123||coreahblite_masterstage.vhd(342);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/342
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(124);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/124||coreahblite_masterstage.vhd(342);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/342
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(125);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/125||coreahblite_masterstage.vhd(343);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/343
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s2 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(126);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/126||coreahblite_masterstage.vhd(343);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/343
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(127);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/127||coreahblite_masterstage.vhd(344);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/344
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s3 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(128);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/128||coreahblite_masterstage.vhd(344);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/344
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(129);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/129||coreahblite_masterstage.vhd(345);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/345
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s4 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(130);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/130||coreahblite_masterstage.vhd(345);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/345
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(131);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/131||coreahblite_masterstage.vhd(346);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/346
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s5 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(132);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/132||coreahblite_masterstage.vhd(346);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/346
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(133);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/133||coreahblite_masterstage.vhd(347);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/347
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s6 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(134);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/134||coreahblite_masterstage.vhd(347);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/347
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(135);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/135||coreahblite_masterstage.vhd(348);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/348
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s7 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(136);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/136||coreahblite_masterstage.vhd(348);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/348
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(137);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/137||coreahblite_masterstage.vhd(349);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/349
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s8 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(138);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/138||coreahblite_masterstage.vhd(349);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/349
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(139);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/139||coreahblite_masterstage.vhd(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/350
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s9 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(140);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/140||coreahblite_masterstage.vhd(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/350
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(141);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/141||coreahblite_masterstage.vhd(351);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/351
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s10 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(142);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/142||coreahblite_masterstage.vhd(351);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/351
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(143);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/143||coreahblite_masterstage.vhd(352);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/352
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s11 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(144);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/144||coreahblite_masterstage.vhd(352);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/352
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(145);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/145||coreahblite_masterstage.vhd(353);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/353
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s12 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(146);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/146||coreahblite_masterstage.vhd(353);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/353
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(147);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/147||coreahblite_masterstage.vhd(354);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/354
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s13 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(148);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/148||coreahblite_masterstage.vhd(354);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/354
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(149);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/149||coreahblite_masterstage.vhd(355);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/355
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s14 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(150);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/150||coreahblite_masterstage.vhd(355);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/355
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(151);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/151||coreahblite_masterstage.vhd(356);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/356
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s15 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(152);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/152||coreahblite_masterstage.vhd(356);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/356
Implementation;Synthesis|| CD434 ||@W:Signal hrdata_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(153);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/153||coreahblite_masterstage.vhd(357);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/357
Implementation;Synthesis|| CD434 ||@W:Signal hreadyout_s16 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.||top.srr(154);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/154||coreahblite_masterstage.vhd(357);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/357
Implementation;Synthesis|| CL177 ||@W:Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.||top.srr(159);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/159||coreahblite_masterstage.vhd(644);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/644
Implementation;Synthesis|| CD274 ||@W:Incomplete case statement - add more cases or a when others||top.srr(165);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/165||AHBMASTER_FIC.vhd(118);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd'/linenumber/118
Implementation;Synthesis|| CL190 ||@W:Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(169);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/169||AHBMASTER_FIC.vhd(106);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd'/linenumber/106
Implementation;Synthesis|| CL260 ||@W:Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(170);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/170||AHBMASTER_FIC.vhd(106);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd'/linenumber/106
Implementation;Synthesis|| CL247 ||@W:Input port bit 0 of htrans(1 downto 0) is unused ||top.srr(193);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/193||CoreAHB2APB.vhd(20);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd'/linenumber/20
Implementation;Synthesis|| CL246 ||@W:Input port bits 16 to 1 of sdataready(16 downto 0) are unused. Assign logic for all port bits or change the input port size.||top.srr(194);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/194||coreahblite_masterstage.vhd(45);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/45
Implementation;Synthesis|| CL246 ||@W:Input port bits 16 to 1 of shresp(16 downto 0) are unused. Assign logic for all port bits or change the input port size.||top.srr(195);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/195||coreahblite_masterstage.vhd(46);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/46
Implementation;Synthesis|| CL247 ||@W:Input port bit 0 of htrans_m0(1 downto 0) is unused ||top.srr(334);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/334||coreahblite.vhd(124);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/124
Implementation;Synthesis|| CL247 ||@W:Input port bit 0 of htrans_m1(1 downto 0) is unused ||top.srr(335);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/335||coreahblite.vhd(135);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/135
Implementation;Synthesis|| CL247 ||@W:Input port bit 0 of htrans_m2(1 downto 0) is unused ||top.srr(336);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/336||coreahblite.vhd(146);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/146
Implementation;Synthesis|| CL247 ||@W:Input port bit 0 of htrans_m3(1 downto 0) is unused ||top.srr(337);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/337||coreahblite.vhd(157);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/157
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s0(1 downto 0) is unused ||top.srr(338);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/338||coreahblite.vhd(167);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/167
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s1(1 downto 0) is unused ||top.srr(339);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/339||coreahblite.vhd(180);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/180
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s2(1 downto 0) is unused ||top.srr(340);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/340||coreahblite.vhd(193);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/193
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s3(1 downto 0) is unused ||top.srr(341);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/341||coreahblite.vhd(206);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/206
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s4(1 downto 0) is unused ||top.srr(342);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/342||coreahblite.vhd(219);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/219
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s5(1 downto 0) is unused ||top.srr(343);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/343||coreahblite.vhd(232);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/232
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s6(1 downto 0) is unused ||top.srr(344);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/344||coreahblite.vhd(245);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/245
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s7(1 downto 0) is unused ||top.srr(345);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/345||coreahblite.vhd(258);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/258
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s8(1 downto 0) is unused ||top.srr(346);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/346||coreahblite.vhd(271);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/271
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s9(1 downto 0) is unused ||top.srr(347);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/347||coreahblite.vhd(284);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/284
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s10(1 downto 0) is unused ||top.srr(348);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/348||coreahblite.vhd(297);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/297
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s11(1 downto 0) is unused ||top.srr(349);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/349||coreahblite.vhd(310);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/310
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s12(1 downto 0) is unused ||top.srr(350);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/350||coreahblite.vhd(323);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/323
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s13(1 downto 0) is unused ||top.srr(351);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/351||coreahblite.vhd(336);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/336
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s14(1 downto 0) is unused ||top.srr(352);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/352||coreahblite.vhd(349);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/349
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s15(1 downto 0) is unused ||top.srr(353);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/353||coreahblite.vhd(362);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/362
Implementation;Synthesis|| CL247 ||@W:Input port bit 1 of hresp_s16(1 downto 0) is unused ||top.srr(354);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/354||coreahblite.vhd(375);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd'/linenumber/375
Implementation;Synthesis|| CL246 ||@W:Input port bits 1 to 0 of paddr(4 downto 0) are unused. Assign logic for all port bits or change the input port size.||top.srr(398);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/398||CoreUARTapb.vhd(83);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd'/linenumber/83
Implementation;Synthesis|| MT530 ||@W:Found inferred clock top|HCLK which controls 472 sequential elements including AHBMASTER_FIC_0.HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance. ||top.srr(552);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/552||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit rx_parity_calc (in view view:coreuartapb_lib.top_CoreUARTapb_0_Rx_async(translated)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(691);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/691||rx_async.vhd(375);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\work\top\coreuartapb_0\rtl\vhdl\core\rx_async.vhd'/linenumber/375
Implementation;Synthesis|| MO160 ||@W:Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] (in view view:work.top(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(699);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/699||coreahblite_masterstage.vhd(305);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\actel\directcore\coreahblite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd'/linenumber/305
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[31] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(709);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/709||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[30] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(710);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/710||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[29] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(711);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/711||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[28] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(712);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/712||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[27] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(713);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/713||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[26] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(714);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/714||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[25] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(715);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/715||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[24] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(716);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/716||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[23] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(717);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/717||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[22] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(718);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/718||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[21] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(719);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/719||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[20] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(720);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/720||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[19] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(721);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/721||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[18] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(722);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/722||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[17] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(723);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/723||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[16] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(724);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/724||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[15] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(725);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/725||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[14] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(726);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/726||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[13] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(727);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/727||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[12] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(728);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/728||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[11] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(729);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/729||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[10] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(730);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/730||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[9] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(731);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/731||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit DATAOUT[8] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(732);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/732||ahbmaster_fic.vhd(106);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd'/linenumber/106
Implementation;Synthesis|| MO160 ||@W:Register bit arbRegSMCurrentState[3] (in view view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_0(coreahblite_slavearbiter_arch)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(827);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/827||coreahblite_slavearbiter.vhd(398);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\actel\directcore\coreahblite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd'/linenumber/398
Implementation;Synthesis|| MO160 ||@W:Register bit arbRegSMCurrentState[7] (in view view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_0(coreahblite_slavearbiter_arch)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(828);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/828||coreahblite_slavearbiter.vhd(398);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\actel\directcore\coreahblite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd'/linenumber/398
Implementation;Synthesis|| MO160 ||@W:Register bit arbRegSMCurrentState[11] (in view view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_0(coreahblite_slavearbiter_arch)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(829);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/829||coreahblite_slavearbiter.vhd(398);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\actel\directcore\coreahblite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd'/linenumber/398
Implementation;Synthesis|| MO160 ||@W:Register bit xmit_state[1] (in view view:coreuartapb_lib.top_CoreUARTapb_0_Tx_async(translated)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(840);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/840||tx_async.vhd(134);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\work\top\coreuartapb_0\rtl\vhdl\core\tx_async.vhd'/linenumber/134
Implementation;Synthesis|| MO161 ||@W:Register bit last_bit[3] (in view view:coreuartapb_lib.top_CoreUARTapb_0_Rx_async(translated)) is always 1. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(852);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/852||rx_async.vhd(241);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\work\top\coreuartapb_0\rtl\vhdl\core\rx_async.vhd'/linenumber/241
Implementation;Synthesis|| MO160 ||@W:Register bit last_bit[2] (in view view:coreuartapb_lib.top_CoreUARTapb_0_Rx_async(translated)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(853);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/853||rx_async.vhd(241);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\work\top\coreuartapb_0\rtl\vhdl\core\rx_async.vhd'/linenumber/241
Implementation;Synthesis|| MO160 ||@W:Register bit last_bit[1] (in view view:coreuartapb_lib.top_CoreUARTapb_0_Rx_async(translated)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.||top.srr(854);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/854||rx_async.vhd(241);liberoaction://cross_probe/hdl/file/'c:\actelprj\test79_ahbmaster\component\work\top\coreuartapb_0\rtl\vhdl\core\rx_async.vhd'/linenumber/241
Implementation;Synthesis|| MT420 ||@W:Found inferred clock top|HCLK with period 10.00ns. Please declare a user-defined clock on object "p:HCLK"||top.srr(1052);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/1052||null;null
Implementation;Synthesis|| MT320 ||@N: This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.||top.srr(1068);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/1068||null;null
Implementation;Synthesis|| MT322 ||@N: Clock constraints include only register-to-register paths associated with each individual clock.||top.srr(1070);liberoaction://cross_probe/hdl/file/'C:\Actelprj\test79_AHBmaster\synthesis\top.srr'/linenumber/1070||null;null