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[/] [amber/] [trunk/] [hw/] [tests/] [irq_disable.S] - Rev 60
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/*****************************************************************// //// Amber 2 Core Interrupt Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests running a simple algorithm to add a bunch of numbers //// and check that the result is correct. This algorithm runs //// 80 times. During this, a whole bunch of IRQ interrupts are //// triggered using the random timer. //// //// The test passes if the add algorithm runs successfully //// each time. //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h".section .text.globl mainmain:/* 0x00 Reset Interrupt vector address */b start/* 0x04 Undefined Instruction Interrupt vector address */b testfail/* 0x08 SWI Interrupt vector address */b testfail/* 0x0c Prefetch abort Interrupt vector address */b testfail/* 0x10 Data abort Interrupt vector address */b testfailb testfail/* 0x18 IRQ vector address */b service_irq/* 0x1c FIRQ vector address */b testfail/* This doesn't actually disabe the irq becauseyou can't disable it uin user mode */disable_irq:orr lr, lr, #0x08000000mov pc, lrstart:/* Set Supervisor Mode stack pointer */ldr sp, AdrSVCStack/* Test that lr is immediately accessible after a mode switch */mov lr, #0x8000mov r0, #0x08000002teqp pc, r0 @ move to irq modenopnop@ Switch back to supervisor modemov r0, #0x08000003teqp pc, r0sub lr, lr, #4 @ access lr immediately after mode switchmov r0, #0x8000sub r0, r0, #4cmp lr, r0movne r10, #200bne testfail/* Switch to IRQ Mode */mov r0, #0x00000002teqp pc, r0/* Set IRQ Mode stack pointer */ldr sp, AdrIRQStack/* Switch to User Mode *//* and unset interrupt mask bits */mov r0, #0x00000000teqp pc, r0bl disable_irq/* Set User Mode stack pointer */ldr sp, AdrUSRStackldr r4, AdrRanNumldr r5, [r4]and r5, r5, #0x1cadd r5, r5, #5ldr r6, AdrIRQTimerstr r5, [r6]mov r2, #0loop:@ set some condition bits@ to test that these get preserved@ correctly through interruptsmov r3, #4subs r3, r3, #4mov r1, #1add r1, r1, #2add r1, r1, #3add r1, r1, #4addeq r1, r1, #5add r1, r1, #6add r1, r1, #7addeq r1, r1, #8add r1, r1, #9add r1, r1, #10add r1, r1, #11add r1, r1, #12mov r7, #13mov r8, #14mov r9, #15stmfd sp!, {r7, r8, r9}mov r7, #0mov r8, #0mov r9, #0ldmfd sp!, {r7, r8, r9}add r1, r1, r7add r1, r1, r8add r1, r1, r9add r1, r1, #16add r1, r1, #17add r1, r1, #18add r1, r1, #19add r1, r1, #20add r1, r1, #21add r1, r1, #22add r1, r1, #23add r1, r1, #24add r1, r1, #25add r1, r1, #26add r1, r1, #27add r1, r1, #28add r1, r1, #29add r1, r1, #30add r1, r1, #47 @ adds up to exactly 512cmp r1, #512movne r10, r2bne testfailcmp r2, #80beq testpassadd r2, r2, #1b loop@ just put these here in case@ the cpu incorrectly executes some instructionsb testfailb testfailb testfailservice_irq:@ Save lr to the stackstmfd sp!, {lr}@ Set the IRQ Timer to a random numberldr r5, [r4]and r5, r5, #0x7f@ Ensure that never set the IRQ timer to zeroadd r5, r5, #30str r5, [r6]@ Restore lr from the stackldmfd sp!, {lr}@ Jump straight back to normal executionsubs pc, lr, #4@ ------------------------------------------@ ------------------------------------------testfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSAdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUMAdrIRQTimer: .word ADR_AMBER_TEST_IRQ_TIMERAdrText1: .word Text1AdrSVCStack: .word 0x0800AdrUSRStack: .word 0x1000AdrIRQStack: .word 0x1800.align 2Text1: .ascii "Interrupt!\n\000"/* ========================================================================= *//* ========================================================================= */