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[/] [audio/] [trunk/] [HD_ADPCM/] [HD_ADPCM_1Bit_Stereo_Decoder/] [HD_ADPCM_Codec.fit.rpt] - Rev 6
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Fitter report for HD_ADPCM_CodecTue May 11 23:49:52 2010Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Fitter Netlist Optimizations6. Incremental Compilation Preservation Summary7. Incremental Compilation Partition Settings8. Incremental Compilation Placement Preservation9. Pin-Out File10. Fitter Resource Usage Summary11. Input Pins12. Output Pins13. Bidir Pins14. I/O Bank Usage15. All Package Pins16. Output Pin Default Load For Reported TCO17. Fitter Resource Utilization by Entity18. Delay Chain Summary19. Pad To Core Delay Chain Fanout20. Control Signals21. Global & Other Fast Signals22. Non-Global High Fan-Out Signals23. Fitter DSP Block Usage Summary24. DSP Block Details25. Interconnect Usage Summary26. LAB Logic Elements27. LAB-wide Signals28. LAB Signals Sourced29. LAB Signals Sourced Out30. LAB Distinct Inputs31. Fitter Device Options32. Operating Settings and Conditions33. Estimated Delay Added for Hold Timing34. Advanced Data - General35. Advanced Data - Placement Preparation36. Advanced Data - Placement37. Advanced Data - Routing38. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2009 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+------------------------------------------------------------------------------+; Fitter Summary ;+------------------------------------+-----------------------------------------+; Fitter Status ; Successful - Tue May 11 23:49:52 2010 ;; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;; Revision Name ; HD_ADPCM_Codec ;; Top-level Entity Name ; HD_ADPCM_Codec ;; Family ; Cyclone II ;; Device ; EP2C20F484C7 ;; Timing Models ; Final ;; Total logic elements ; 1,663 / 18,752 ( 9 % ) ;; Total combinational functions ; 1,635 / 18,752 ( 9 % ) ;; Dedicated logic registers ; 364 / 18,752 ( 2 % ) ;; Total registers ; 364 ;; Total pins ; 82 / 315 ( 26 % ) ;; Total virtual pins ; 0 ;; Total memory bits ; 0 / 239,616 ( 0 % ) ;; Embedded Multiplier 9-bit elements ; 4 / 52 ( 8 % ) ;; Total PLLs ; 0 / 4 ( 0 % ) ;+------------------------------------+-----------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+--------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+--------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; EP2C20F484C7 ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Device I/O Standard ; 3.3-V LVCMOS ; ;; Use smart compilation ; Off ; Off ;; Use TimeQuest Timing Analyzer ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Multi-Corner Timing ; Off ; Off ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate full fit report during ECO compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Merge PLLs ; On ; On ;; Ignore PLL Mode When Merging PLLs ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Stop After Congestion Map Generation ; Off ; Off ;; Save Intermediate Fitting Results ; Off ; Off ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;+--------------------------------------------------------------------+--------------------------------+--------------------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 2 ;; Maximum allowed ; 1 ;+----------------------------+--------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Netlist Optimizations ;+------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+------------------------------------------------------------------------------+------------------+-----------------------+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;+------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+------------------------------------------------------------------------------+------------------+-----------------------+; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[0] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[1] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[2] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[3] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[4] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[5] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[6] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[7] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[8] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[0] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[0]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[1] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[1]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[2] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[2]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[3] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[3]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[5] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[5]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[6] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[6]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[7] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[7]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[8] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[8]~_Duplicate_2 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAB ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_1 ; REGOUT ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; DATAA ; ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]~_Duplicate_2 ; REGOUT ; ;+------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+------------------------------------------------------------------------------+------------------+-----------------------++-----------------------------------------------+; Incremental Compilation Preservation Summary ;+-------------------------+---------------------+; Type ; Value ;+-------------------------+---------------------+; Placement ; ;; -- Requested ; 0 / 2083 ( 0.00 % ) ;; -- Achieved ; 0 / 2083 ( 0.00 % ) ;; ; ;; Routing (by Connection) ; ;; -- Requested ; 0 / 0 ( 0.00 % ) ;; -- Achieved ; 0 / 0 ( 0.00 % ) ;+-------------------------+---------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Partition Settings ;+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------++--------------------------------------------------------------------------------------------+; Incremental Compilation Placement Preservation ;+----------------+---------+-------------------+-------------------------+-------------------+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;+----------------+---------+-------------------+-------------------------+-------------------+; Top ; 2083 ; 0 ; N/A ; Source File ;+----------------+---------+-------------------+-------------------------+-------------------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/HD_ADPCM_Codec.pin.+-----------------------------------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+---------------------------------------------+-------------------------------------------------------+; Resource ; Usage ;+---------------------------------------------+-------------------------------------------------------+; Total logic elements ; 1,663 / 18,752 ( 9 % ) ;; -- Combinational with no register ; 1299 ;; -- Register only ; 28 ;; -- Combinational with a register ; 336 ;; ; ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 384 ;; -- 3 input functions ; 307 ;; -- <=2 input functions ; 944 ;; -- Register only ; 28 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 1058 ;; -- arithmetic mode ; 577 ;; ; ;; Total registers* ; 364 / 19,649 ( 2 % ) ;; -- Dedicated logic registers ; 364 / 18,752 ( 2 % ) ;; -- I/O registers ; 0 / 897 ( 0 % ) ;; ; ;; Total LABs: partially or completely used ; 148 / 1,172 ( 13 % ) ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 82 / 315 ( 26 % ) ;; -- Clock pins ; 2 / 8 ( 25 % ) ;; Global signals ; 4 ;; M4Ks ; 0 / 52 ( 0 % ) ;; Total block memory bits ; 0 / 239,616 ( 0 % ) ;; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ;; Embedded Multiplier 9-bit elements ; 4 / 52 ( 8 % ) ;; PLLs ; 0 / 4 ( 0 % ) ;; Global clocks ; 4 / 16 ( 25 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; ASMI blocks ; 0 / 1 ( 0 % ) ;; CRC blocks ; 0 / 1 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 2% / 1% / 2% ;; Peak interconnect usage (total/H/V) ; 6% / 6% / 6% ;; Maximum fan-out node ; CLOCK_IN~clkctrl ;; Maximum fan-out ; 287 ;; Highest non-global fan-out signal ; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_State_Counter[0] ;; Highest non-global fan-out ; 44 ;; Total fan-out ; 5431 ;; Average fan-out ; 2.58 ;+---------------------------------------------+-------------------------------------------------------+* Register count does not include registers inside RAM blocks or DSP blocks.+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; CLOCK_IN ; D12 ; 3 ; 24 ; 27 ; 2 ; 4 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;; KEY_0 ; R22 ; 6 ; 50 ; 10 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;; KEY_1 ; R21 ; 6 ; 50 ; 10 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;; SWITCH_0 ; L22 ; 5 ; 50 ; 14 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+------------------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;+------------------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; FLASH_MEMORY_ADDRESS_OUT[0] ; AB20 ; 7 ; 48 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[10] ; R12 ; 7 ; 33 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[11] ; T12 ; 7 ; 31 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[12] ; AB14 ; 7 ; 33 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[13] ; AA13 ; 7 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[14] ; AB13 ; 7 ; 29 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[15] ; AA12 ; 7 ; 29 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[16] ; AB12 ; 7 ; 29 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[17] ; AA20 ; 7 ; 48 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[18] ; U14 ; 7 ; 39 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[19] ; V14 ; 7 ; 37 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[1] ; AA14 ; 7 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[20] ; U13 ; 7 ; 31 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[21] ; R13 ; 7 ; 37 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[2] ; Y16 ; 7 ; 44 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[3] ; R15 ; 7 ; 42 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[4] ; T15 ; 7 ; 39 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[5] ; U15 ; 7 ; 46 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[6] ; V15 ; 7 ; 46 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[7] ; W15 ; 7 ; 39 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[8] ; R14 ; 7 ; 42 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_ADDRESS_OUT[9] ; Y13 ; 7 ; 31 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_nCE_OUT ; AB15 ; 7 ; 33 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_nOE_OUT ; AA15 ; 7 ; 35 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_nRESET_OUT ; W14 ; 7 ; 35 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_nWE_OUT ; Y14 ; 7 ; 39 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; I2C_CLOCK_OUT ; A3 ; 3 ; 1 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; I2S_CLOCK_OUT ; A4 ; 3 ; 1 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; I2S_CORE_CLOCK_OUT ; B4 ; 3 ; 1 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; I2S_LEFT_RIGHT_CLOCK_OUT ; A5 ; 3 ; 3 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[0] ; R20 ; 6 ; 50 ; 10 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[1] ; R19 ; 6 ; 50 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[2] ; U19 ; 6 ; 50 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[3] ; Y19 ; 6 ; 50 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[4] ; T18 ; 6 ; 50 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[5] ; V19 ; 6 ; 50 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[6] ; Y18 ; 6 ; 50 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[7] ; U18 ; 6 ; 50 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[8] ; R18 ; 6 ; 50 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_RED_LEDS_OUT[9] ; R17 ; 6 ; 50 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[0] ; J2 ; 2 ; 0 ; 18 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[1] ; J1 ; 2 ; 0 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[2] ; H2 ; 2 ; 0 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[3] ; H1 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[4] ; F2 ; 2 ; 0 ; 20 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[5] ; F1 ; 2 ; 0 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_1_OUT[6] ; E2 ; 2 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[0] ; E1 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[1] ; H6 ; 2 ; 0 ; 21 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[2] ; H5 ; 2 ; 0 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[3] ; H4 ; 2 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[4] ; G3 ; 2 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[5] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_2_OUT[6] ; D1 ; 2 ; 0 ; 22 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[0] ; G5 ; 2 ; 0 ; 22 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[1] ; G6 ; 2 ; 0 ; 23 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[2] ; C2 ; 2 ; 0 ; 23 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[3] ; C1 ; 2 ; 0 ; 23 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[4] ; E3 ; 2 ; 0 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[5] ; E4 ; 2 ; 0 ; 24 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_3_OUT[6] ; D3 ; 2 ; 0 ; 25 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[0] ; F4 ; 2 ; 0 ; 23 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[1] ; D5 ; 2 ; 0 ; 24 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[2] ; D6 ; 2 ; 0 ; 24 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[3] ; J4 ; 2 ; 0 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[4] ; L8 ; 2 ; 0 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[5] ; F3 ; 2 ; 0 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;; S_SEVEN_SEGMENT_4_OUT[6] ; D4 ; 2 ; 0 ; 25 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 0 pF ;+------------------------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Bidir Pins ;+----------------------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;+----------------------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; FLASH_MEMORY_DATA_INOUT[0] ; AB16 ; 7 ; 35 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[1] ; AA16 ; 7 ; 35 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[2] ; AB17 ; 7 ; 37 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[3] ; AA17 ; 7 ; 37 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[4] ; AB18 ; 7 ; 42 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[5] ; AA18 ; 7 ; 44 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[6] ; AB19 ; 7 ; 48 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; FLASH_MEMORY_DATA_INOUT[7] ; AA19 ; 7 ; 48 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; I2C_DATA_INOUT ; B3 ; 3 ; 1 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;; I2S_DATA_INOUT ; B5 ; 3 ; 3 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 24mA ; Off ; User ; 0 pF ;+----------------------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 0 / 41 ( 0 % ) ; 3.3V ; -- ;; 2 ; 30 / 33 ( 91 % ) ; 3.3V ; -- ;; 3 ; 7 / 43 ( 16 % ) ; 3.3V ; -- ;; 4 ; 0 / 40 ( 0 % ) ; 3.3V ; -- ;; 5 ; 1 / 39 ( 3 % ) ; 3.3V ; -- ;; 6 ; 13 / 36 ( 36 % ) ; 3.3V ; -- ;; 7 ; 34 / 40 ( 85 % ) ; 3.3V ; -- ;; 8 ; 0 / 43 ( 0 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A3 ; 325 ; 3 ; I2C_CLOCK_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; A4 ; 324 ; 3 ; I2S_CLOCK_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; A5 ; 322 ; 3 ; I2S_LEFT_RIGHT_CLOCK_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; A6 ; 320 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A7 ; 306 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A8 ; 304 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A9 ; 298 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A10 ; 293 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A11 ; 287 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; A13 ; 281 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A14 ; 279 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A15 ; 273 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A16 ; 271 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A17 ; 265 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A18 ; 251 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A19 ; 249 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A20 ; 247 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA3 ; 82 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA4 ; 85 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA5 ; 89 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA6 ; 97 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA7 ; 103 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA8 ; 111 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA9 ; 114 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA10 ; 120 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA11 ; 122 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AA12 ; 128 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[15] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA13 ; 130 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[13] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA14 ; 136 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA15 ; 138 ; 7 ; FLASH_MEMORY_nOE_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA16 ; 140 ; 7 ; FLASH_MEMORY_DATA_INOUT[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA17 ; 144 ; 7 ; FLASH_MEMORY_DATA_INOUT[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA18 ; 153 ; 7 ; FLASH_MEMORY_DATA_INOUT[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA19 ; 162 ; 7 ; FLASH_MEMORY_DATA_INOUT[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA20 ; 164 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[17] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB3 ; 83 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB4 ; 84 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB5 ; 88 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB6 ; 96 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB7 ; 102 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB8 ; 110 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB9 ; 113 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB10 ; 119 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB11 ; 121 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; AB12 ; 127 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[16] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB13 ; 129 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[14] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB14 ; 135 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[12] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB15 ; 137 ; 7 ; FLASH_MEMORY_nCE_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB16 ; 139 ; 7 ; FLASH_MEMORY_DATA_INOUT[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB17 ; 143 ; 7 ; FLASH_MEMORY_DATA_INOUT[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB18 ; 152 ; 7 ; FLASH_MEMORY_DATA_INOUT[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB19 ; 161 ; 7 ; FLASH_MEMORY_DATA_INOUT[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB20 ; 163 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B3 ; 326 ; 3 ; I2C_DATA_INOUT ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; B4 ; 323 ; 3 ; I2S_CORE_CLOCK_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; B5 ; 321 ; 3 ; I2S_DATA_INOUT ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; B6 ; 319 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B7 ; 305 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B8 ; 303 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B9 ; 297 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B10 ; 292 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B11 ; 286 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; B13 ; 280 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B14 ; 278 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B15 ; 272 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B16 ; 270 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B17 ; 264 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B18 ; 250 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B19 ; 248 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B20 ; 246 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C1 ; 8 ; 2 ; S_SEVEN_SEGMENT_3_OUT[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; C2 ; 9 ; 2 ; S_SEVEN_SEGMENT_3_OUT[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C7 ; 315 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C9 ; 310 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C10 ; 296 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C13 ; 275 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C14 ; 260 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; C16 ; 254 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C17 ; 245 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C18 ; 244 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; C19 ; 238 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; C20 ; 239 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; C21 ; 236 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; C22 ; 237 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; D1 ; 14 ; 2 ; S_SEVEN_SEGMENT_2_OUT[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; D2 ; 15 ; 2 ; S_SEVEN_SEGMENT_2_OUT[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; D3 ; 2 ; 2 ; S_SEVEN_SEGMENT_3_OUT[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; D4 ; 3 ; 2 ; S_SEVEN_SEGMENT_4_OUT[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; D5 ; 4 ; 2 ; S_SEVEN_SEGMENT_4_OUT[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; D6 ; 5 ; 2 ; S_SEVEN_SEGMENT_4_OUT[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; D7 ; 311 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D8 ; 309 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D9 ; 302 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D11 ; 289 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D12 ; 284 ; 3 ; CLOCK_IN ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D14 ; 267 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D15 ; 259 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D16 ; 255 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; D19 ; 240 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; D20 ; 241 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; D21 ; 229 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; D22 ; 230 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; E1 ; 20 ; 2 ; S_SEVEN_SEGMENT_2_OUT[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; E2 ; 21 ; 2 ; S_SEVEN_SEGMENT_1_OUT[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; E3 ; 6 ; 2 ; S_SEVEN_SEGMENT_3_OUT[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; E4 ; 7 ; 2 ; S_SEVEN_SEGMENT_3_OUT[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; E7 ; 316 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; E8 ; 308 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; E9 ; 301 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; E11 ; 288 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; E14 ; 266 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; E15 ; 256 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; E18 ; 243 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; E19 ; 242 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; E20 ; 234 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; E21 ; 227 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; E22 ; 228 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; F1 ; 22 ; 2 ; S_SEVEN_SEGMENT_1_OUT[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; F2 ; 23 ; 2 ; S_SEVEN_SEGMENT_1_OUT[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; F3 ; 13 ; 2 ; S_SEVEN_SEGMENT_4_OUT[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; F4 ; 10 ; 2 ; S_SEVEN_SEGMENT_4_OUT[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; F8 ; 312 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F9 ; 307 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F10 ; 295 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F11 ; 294 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F12 ; 276 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F13 ; 269 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F14 ; 268 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F15 ; 262 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; F20 ; 235 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; F21 ; 223 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; F22 ; 224 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; G3 ; 16 ; 2 ; S_SEVEN_SEGMENT_2_OUT[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G5 ; 12 ; 2 ; S_SEVEN_SEGMENT_3_OUT[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; G6 ; 11 ; 2 ; S_SEVEN_SEGMENT_3_OUT[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; G7 ; 317 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; G8 ; 313 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G11 ; 291 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; G12 ; 277 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G15 ; 261 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; G16 ; 252 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; G17 ; 231 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; G18 ; 232 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G20 ; 233 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; G21 ; 221 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; G22 ; 222 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; H1 ; 24 ; 2 ; S_SEVEN_SEGMENT_1_OUT[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; H2 ; 25 ; 2 ; S_SEVEN_SEGMENT_1_OUT[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; H3 ; 27 ; 2 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; H4 ; 17 ; 2 ; S_SEVEN_SEGMENT_2_OUT[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; H5 ; 18 ; 2 ; S_SEVEN_SEGMENT_2_OUT[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; H6 ; 19 ; 2 ; S_SEVEN_SEGMENT_2_OUT[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; H7 ; 318 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H8 ; 314 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H9 ; 300 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H10 ; 299 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H11 ; 290 ; 3 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H12 ; 274 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H13 ; 263 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H14 ; 257 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H15 ; 253 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; H16 ; 219 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; H17 ; 226 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; H18 ; 225 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; H19 ; 214 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J1 ; 29 ; 2 ; S_SEVEN_SEGMENT_1_OUT[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; J2 ; 30 ; 2 ; S_SEVEN_SEGMENT_1_OUT[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J4 ; 28 ; 2 ; S_SEVEN_SEGMENT_4_OUT[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J14 ; 258 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; J15 ; 220 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; J17 ; 218 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; J18 ; 217 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; J19 ; 216 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; J20 ; 213 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; J21 ; 211 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; J22 ; 212 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K20 ; 215 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; K21 ; 209 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; K22 ; 210 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L8 ; 26 ; 2 ; S_SEVEN_SEGMENT_4_OUT[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; L18 ; 208 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; L19 ; 207 ; 5 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; L22 ; 206 ; 5 ; SWITCH_0 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; M1 ; 41 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; M2 ; 42 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M5 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; M6 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; M18 ; 202 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; M19 ; 201 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; N1 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N2 ; 46 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N3 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N4 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; N6 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N15 ; 194 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; N21 ; 199 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; N22 ; 200 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P1 ; 47 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P2 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P3 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P5 ; 55 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P6 ; 56 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P8 ; 95 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; P9 ; 94 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P15 ; 193 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P17 ; 186 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P18 ; 187 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; R1 ; 57 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; R2 ; 58 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; R5 ; 63 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; R6 ; 64 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; R7 ; 54 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; R8 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; R9 ; 109 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; R10 ; 108 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; R11 ; 116 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; R12 ; 134 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[10] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; R13 ; 145 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[21] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; R14 ; 150 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[8] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; R15 ; 151 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; R16 ; 155 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; R17 ; 177 ; 6 ; S_RED_LEDS_OUT[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; R18 ; 184 ; 6 ; S_RED_LEDS_OUT[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; R19 ; 185 ; 6 ; S_RED_LEDS_OUT[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; R20 ; 192 ; 6 ; S_RED_LEDS_OUT[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; R21 ; 190 ; 6 ; KEY_1 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; R22 ; 191 ; 6 ; KEY_0 ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; T1 ; 59 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; T2 ; 60 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; T3 ; 69 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T5 ; 67 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; T6 ; 68 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; T7 ; 91 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; T8 ; 90 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T11 ; 115 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; T12 ; 131 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[11] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T15 ; 147 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; T16 ; 156 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; T18 ; 171 ; 6 ; S_RED_LEDS_OUT[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; T21 ; 188 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; T22 ; 189 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U1 ; 61 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U2 ; 62 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U3 ; 70 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U4 ; 80 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U8 ; 92 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; U9 ; 106 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; U10 ; 107 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; U13 ; 132 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[20] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; U14 ; 146 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[18] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; U15 ; 157 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U18 ; 170 ; 6 ; S_RED_LEDS_OUT[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; U19 ; 172 ; 6 ; S_RED_LEDS_OUT[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; U20 ; 176 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U21 ; 182 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; U22 ; 183 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; V1 ; 65 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; V2 ; 66 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V4 ; 81 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; V8 ; 98 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; V9 ; 101 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; V11 ; 118 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; V14 ; 142 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[19] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; V15 ; 158 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; V19 ; 166 ; 6 ; S_RED_LEDS_OUT[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; V20 ; 173 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; V21 ; 180 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; V22 ; 181 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W1 ; 71 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W2 ; 72 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W3 ; 75 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W4 ; 76 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W5 ; 79 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; W7 ; 99 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; W8 ; 100 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; W9 ; 105 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W11 ; 117 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W14 ; 141 ; 7 ; FLASH_MEMORY_nRESET_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; W15 ; 149 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; W16 ; 160 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;; W21 ; 174 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; W22 ; 175 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y1 ; 73 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y2 ; 74 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y3 ; 77 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y4 ; 78 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y5 ; 86 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; Y6 ; 87 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; Y7 ; 93 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y9 ; 104 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; Y10 ; 112 ; 8 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; Y13 ; 133 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[9] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; Y14 ; 148 ; 7 ; FLASH_MEMORY_nWE_OUT ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; Y16 ; 154 ; 7 ; FLASH_MEMORY_ADDRESS_OUT[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;; Y17 ; 159 ; 7 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;; Y18 ; 165 ; 6 ; S_RED_LEDS_OUT[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; Y19 ; 168 ; 6 ; S_RED_LEDS_OUT[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;; Y20 ; 169 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y21 ; 178 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;; Y22 ; 179 ; 6 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------------+-------+------------------------------------+; 3.3-V LVTTL ; 0 pF ; Not Available ;; 3.3-V LVCMOS ; 0 pF ; Not Available ;; 2.5 V ; 0 pF ; Not Available ;; 1.8 V ; 0 pF ; Not Available ;; 1.5 V ; 0 pF ; Not Available ;; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;; LVDS ; 0 pF ; 100 Ohm (Differential) ;; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;; RSDS ; 0 pF ; 100 Ohm (Differential) ;; Simple RSDS ; 0 pF ; Not Available ;; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;+----------------------------------+-------+------------------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+; |HD_ADPCM_Codec ; 1663 (110) ; 364 (82) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 82 ; 0 ; 1299 (28) ; 28 (0) ; 336 (84) ; |HD_ADPCM_Codec ; work ;; |ADPCM_Decoder_1_Bit:u5| ; 669 (380) ; 74 (74) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 593 (305) ; 0 (0) ; 76 (75) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5 ; work ;; |lpm_divide:Div0| ; 289 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (0) ; 0 (0) ; 1 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0 ; work ;; |lpm_divide_aem:auto_generated| ; 289 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (0) ; 0 (0) ; 1 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated ; work ;; |sign_div_unsign_klh:divider| ; 289 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (0) ; 0 (0) ; 1 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider ; work ;; |alt_u_div_e2f:divider| ; 289 (289) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (288) ; 0 (0) ; 1 (1) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider ; work ;; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0 ; work ;; |mult_pu01:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated ; work ;; |ADPCM_Decoder_1_Bit:u6| ; 661 (372) ; 77 (77) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 584 (296) ; 0 (0) ; 77 (76) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6 ; work ;; |lpm_divide:Div0| ; 289 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (0) ; 0 (0) ; 1 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0 ; work ;; |lpm_divide_aem:auto_generated| ; 289 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (0) ; 0 (0) ; 1 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated ; work ;; |sign_div_unsign_klh:divider| ; 289 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (0) ; 0 (0) ; 1 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider ; work ;; |alt_u_div_e2f:divider| ; 289 (289) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 288 (288) ; 0 (0) ; 1 (1) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider ; work ;; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0 ; work ;; |mult_pu01:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated ; work ;; |Flash_Memory_Driver:u4| ; 71 (71) ; 61 (61) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 28 (28) ; 33 (33) ; |HD_ADPCM_Codec|Flash_Memory_Driver:u4 ; work ;; |I2C_Driver:u2| ; 72 (72) ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 38 (38) ; 0 (0) ; 34 (34) ; |HD_ADPCM_Codec|I2C_Driver:u2 ; work ;; |I2S_Driver:u3| ; 73 (73) ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 (37) ; 0 (0) ; 36 (36) ; |HD_ADPCM_Codec|I2S_Driver:u3 ; work ;; |LEDs_Bar_Driver:u1| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 0 (0) ; |HD_ADPCM_Codec|LEDs_Bar_Driver:u1 ; work ;+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-------------------------------------------------------------------------------------------------------+; Delay Chain Summary ;+------------------------------+----------+---------------+---------------+-----------------------+-----+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;+------------------------------+----------+---------------+---------------+-----------------------+-----+; I2C_DATA_INOUT ; Bidir ; 0 ; 0 ; -- ; -- ;; I2S_DATA_INOUT ; Bidir ; 0 ; 0 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[0] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[1] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[2] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[3] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[4] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[5] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[6] ; Bidir ; 6 ; 6 ; -- ; -- ;; FLASH_MEMORY_DATA_INOUT[7] ; Bidir ; 6 ; 6 ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[0] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[1] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[2] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[3] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[4] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[5] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_1_OUT[6] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[0] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[1] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[2] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[3] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[4] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[5] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_2_OUT[6] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[0] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[1] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[2] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[3] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[4] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[5] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_3_OUT[6] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[0] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[1] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[2] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[3] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[4] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[5] ; Output ; -- ; -- ; -- ; -- ;; S_SEVEN_SEGMENT_4_OUT[6] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[0] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[1] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[2] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[3] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[4] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[5] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[6] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[7] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[8] ; Output ; -- ; -- ; -- ; -- ;; S_RED_LEDS_OUT[9] ; Output ; -- ; -- ; -- ; -- ;; I2C_CLOCK_OUT ; Output ; -- ; -- ; -- ; -- ;; I2S_LEFT_RIGHT_CLOCK_OUT ; Output ; -- ; -- ; -- ; -- ;; I2S_CLOCK_OUT ; Output ; -- ; -- ; -- ; -- ;; I2S_CORE_CLOCK_OUT ; Output ; -- ; -- ; -- ; -- ;; SWITCH_0 ; Input ; 0 ; 0 ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[0] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[1] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[2] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[3] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[4] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[5] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[6] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[7] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[8] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[9] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[10] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[11] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[12] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[13] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[14] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[15] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[16] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[17] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[18] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[19] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[20] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_ADDRESS_OUT[21] ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_nWE_OUT ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_nOE_OUT ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_nRESET_OUT ; Output ; -- ; -- ; -- ; -- ;; FLASH_MEMORY_nCE_OUT ; Output ; -- ; -- ; -- ; -- ;; CLOCK_IN ; Input ; 0 ; 0 ; -- ; -- ;; KEY_0 ; Input ; 6 ; 6 ; -- ; -- ;; KEY_1 ; Input ; 6 ; 6 ; -- ; -- ;+------------------------------+----------+---------------+---------------+-----------------------+-----++---------------------------------------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+---------------------------------------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+---------------------------------------------------------------+-------------------+---------+; I2C_DATA_INOUT ; ; ;; I2S_DATA_INOUT ; ; ;; FLASH_MEMORY_DATA_INOUT[0] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[0] ; 0 ; 6 ;; FLASH_MEMORY_DATA_INOUT[1] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[1] ; 0 ; 6 ;; FLASH_MEMORY_DATA_INOUT[2] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[2] ; 1 ; 6 ;; FLASH_MEMORY_DATA_INOUT[3] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[3] ; 0 ; 6 ;; FLASH_MEMORY_DATA_INOUT[4] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[4] ; 0 ; 6 ;; FLASH_MEMORY_DATA_INOUT[5] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[5]~feeder ; 0 ; 6 ;; FLASH_MEMORY_DATA_INOUT[6] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[6]~feeder ; 0 ; 6 ;; FLASH_MEMORY_DATA_INOUT[7] ; ; ;; - Flash_Memory_Driver:u4|FLASH_MEMORY_DATA_OUT[7]~feeder ; 0 ; 6 ;; SWITCH_0 ; ; ;; CLOCK_IN ; ; ;; KEY_0 ; ; ;; - Add3~16 ; 1 ; 6 ;; - Add3~14 ; 1 ; 6 ;; - Add3~8 ; 1 ; 6 ;; - Add3~6 ; 1 ; 6 ;; - Add3~10 ; 1 ; 6 ;; - Add3~12 ; 1 ; 6 ;; - Add3~2 ; 1 ; 6 ;; - AUDIO_CODEC_VOLUME[6]~30 ; 1 ; 6 ;; KEY_1 ; ; ;; - AUDIO_CODEC_VOLUME[6]~30 ; 0 ; 6 ;+---------------------------------------------------------------+-------------------+---------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+--------------------------------------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+--------------------------------------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9]~45 ; LCCOMB_X34_Y17_N30 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u5|Last_PCM_Data[15]~17 ; LCCOMB_X37_Y12_N28 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u5|PCM_DATA_OUT[15]~5 ; LCCOMB_X37_Y12_N6 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u5|PCM_Data[15]~182 ; LCCOMB_X37_Y12_N16 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[0]~1 ; LCCOMB_X34_Y17_N22 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u5|process_0~0 ; LCCOMB_X36_Y13_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_State_Counter[0] ; LCFF_X29_Y19_N1 ; 44 ; Sync. load ; no ; -- ; -- ; -- ;; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]~45 ; LCCOMB_X29_Y19_N26 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; AUDIO_CODEC_VOLUME[6]~30 ; LCCOMB_X14_Y12_N30 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;; CLOCK_IN ; PIN_D12 ; 4 ; Clock ; no ; -- ; -- ; -- ;; CLOCK_IN ; PIN_D12 ; 287 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ;; Equal0~0 ; LCCOMB_X36_Y1_N14 ; 21 ; Clock enable ; no ; -- ; -- ; -- ;; Equal1~7 ; LCCOMB_X15_Y12_N30 ; 43 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;; Flash_Memory_Driver:u4|Equal0~7 ; LCCOMB_X15_Y10_N30 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ;; Flash_Memory_Driver:u4|FLASH_MEMORY_ADDRESS[14]~0 ; LCCOMB_X34_Y1_N14 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;; Flash_Memory_Driver:u4|Flash_Memory_Clock ; LCFF_X15_Y12_N9 ; 35 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;; Flash_Memory_Driver:u4|Mux33~0 ; LCCOMB_X36_Y1_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; I2C_ACTIVE_IN ; LCFF_X16_Y13_N1 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ;; I2C_Driver:u2|Equal0~7 ; LCCOMB_X19_Y10_N6 ; 32 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;; I2S_ACTIVE_IN ; LCFF_X15_Y12_N5 ; 2 ; Async. clear, Clock ; no ; -- ; -- ; -- ;; I2S_Driver:u3|Equal0~7 ; LCCOMB_X23_Y15_N30 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ;; I2S_Driver:u3|I2S_Clock ; LCFF_X24_Y15_N29 ; 4 ; Clock ; no ; -- ; -- ; -- ;; I2S_Driver:u3|I2S_Clock ; LCFF_X24_Y15_N29 ; 8 ; Clock ; yes ; Global Clock ; GCLK9 ; -- ;; I2S_Driver:u3|I2S_PCM_DATA_ACCESS_OUT ; LCFF_X29_Y13_N9 ; 31 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;+--------------------------------------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+-------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-------------------------------------------+------------------+---------+----------------------+------------------+---------------------------+; CLOCK_IN ; PIN_D12 ; 287 ; Global Clock ; GCLK11 ; -- ;; Flash_Memory_Driver:u4|Flash_Memory_Clock ; LCFF_X15_Y12_N9 ; 35 ; Global Clock ; GCLK0 ; -- ;; I2S_Driver:u3|I2S_Clock ; LCFF_X24_Y15_N29 ; 8 ; Global Clock ; GCLK9 ; -- ;; I2S_Driver:u3|I2S_PCM_DATA_ACCESS_OUT ; LCFF_X29_Y13_N9 ; 31 ; Global Clock ; GCLK3 ; -- ;+-------------------------------------------+------------------+---------+----------------------+------------------+---------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+----------------------------------------------------------------------------------------------------------------------------------------------------+---------+; Name ; Fan-Out ;+----------------------------------------------------------------------------------------------------------------------------------------------------+---------+; ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_State_Counter[0] ; 44 ;; Equal1~7 ; 43 ;; ADPCM_Decoder_1_Bit:u5|Last_PCM_Data[15]~17 ; 34 ;; ADPCM_Decoder_1_Bit:u5|PCM_Data[15]~182 ; 34 ;; ADPCM_Decoder_1_Bit:u5|PCM_DATA_OUT[15]~5 ; 32 ;; I2C_Driver:u2|Equal0~7 ; 32 ;; ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[0]~1 ; 29 ;; Flash_Memory_Driver:u4|Equal0~7 ; 26 ;; I2S_Driver:u3|Equal0~7 ; 26 ;; Flash_Memory_Driver:u4|FLASH_MEMORY_ADDRESS[14]~0 ; 22 ;; Equal0~0 ; 21 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_14_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_14_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[8]~12 ; 20 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[8]~12 ; 20 ;; ADPCM_DECODER_DATA_RIGHT ; 19 ;; ADPCM_DECODER_DATA_LEFT ; 19 ;; ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[7]~10 ; 19 ;; ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[7]~10 ; 19 ;; ADPCM_Decoder_1_Bit:u6|LessThan17~4 ; 17 ;; ADPCM_Decoder_1_Bit:u6|LessThan15~5 ; 17 ;; ADPCM_Decoder_1_Bit:u5|Mux45~4 ; 17 ;; ADPCM_Decoder_1_Bit:u5|PCM_Data~171 ; 17 ;; ADPCM_Decoder_1_Bit:u6|LessThan16~5 ; 16 ;; ADPCM_Decoder_1_Bit:u6|LessThan14~4 ; 16 ;; ADPCM_Decoder_1_Bit:u5|LessThan16~5 ; 16 ;; ADPCM_Decoder_1_Bit:u5|LessThan14~4 ; 16 ;; I2C_Driver:u2|I2C_Stream_Counter[1] ; 16 ;; I2C_Stream_Counter[1] ; 15 ;; ADPCM_Decoder_1_Bit:u6|LessThan13~3 ; 14 ;; I2C_Stream_Counter[2] ; 14 ;; I2C_Stream_Counter[0] ; 14 ;+----------------------------------------------------------------------------------------------------------------------------------------------------+---------++-----------------------------------------------------------------------------------------------+; Fitter DSP Block Usage Summary ;+---------------------------------------+-------------+---------------------+-------------------+; Statistic ; Number Used ; Available per Block ; Maximum Available ;+---------------------------------------+-------------+---------------------+-------------------+; Simple Multipliers (9-bit) ; 0 ; 2 ; 52 ;; Simple Multipliers (18-bit) ; 2 ; 1 ; 26 ;; Embedded Multiplier Blocks ; 2 ; -- ; 26 ;; Embedded Multiplier 9-bit elements ; 4 ; 2 ; 52 ;; Signed Embedded Multipliers ; 0 ; -- ; -- ;; Unsigned Embedded Multipliers ; 2 ; -- ; -- ;; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ;; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ;; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ;+---------------------------------------+-------------+---------------------+-------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DSP Block Details ;+-----------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ;+-----------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X28_Y14_N2 ; ; No ; ; ; ; no ;; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; ; DSPMULT_X28_Y14_N0 ; Variable ; ; yes ; yes ; no ; ;; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X28_Y17_N2 ; ; No ; ; ; ; no ;; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1 ; ; DSPMULT_X28_Y17_N0 ; Variable ; ; yes ; yes ; no ; ;+-----------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------++-----------------------------------------------------+; Interconnect Usage Summary ;+----------------------------+------------------------+; Interconnect Resource Type ; Usage ;+----------------------------+------------------------+; Block interconnects ; 1,888 / 54,004 ( 3 % ) ;; C16 interconnects ; 1 / 2,100 ( < 1 % ) ;; C4 interconnects ; 917 / 36,000 ( 3 % ) ;; Direct links ; 578 / 54,004 ( 1 % ) ;; Global clocks ; 4 / 16 ( 25 % ) ;; Local interconnects ; 788 / 18,752 ( 4 % ) ;; R24 interconnects ; 9 / 1,900 ( < 1 % ) ;; R4 interconnects ; 938 / 46,920 ( 2 % ) ;+----------------------------+------------------------++-----------------------------------------------------------------------------+; LAB Logic Elements ;+---------------------------------------------+-------------------------------+; Number of Logic Elements (Average = 11.24) ; Number of LABs (Total = 148) ;+---------------------------------------------+-------------------------------+; 1 ; 19 ;; 2 ; 6 ;; 3 ; 12 ;; 4 ; 4 ;; 5 ; 3 ;; 6 ; 4 ;; 7 ; 3 ;; 8 ; 2 ;; 9 ; 0 ;; 10 ; 0 ;; 11 ; 0 ;; 12 ; 1 ;; 13 ; 3 ;; 14 ; 1 ;; 15 ; 1 ;; 16 ; 89 ;+---------------------------------------------+-------------------------------++--------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+-------------------------------+; LAB-wide Signals (Average = 0.77) ; Number of LABs (Total = 148) ;+------------------------------------+-------------------------------+; 1 Clock ; 56 ;; 1 Clock enable ; 28 ;; 1 Sync. clear ; 5 ;; 1 Sync. load ; 9 ;; 2 Clock enables ; 10 ;; 2 Clocks ; 6 ;+------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+-------------------------------+; Number of Signals Sourced (Average = 13.34) ; Number of LABs (Total = 148) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 12 ;; 2 ; 12 ;; 3 ; 12 ;; 4 ; 4 ;; 5 ; 3 ;; 6 ; 3 ;; 7 ; 3 ;; 8 ; 2 ;; 9 ; 1 ;; 10 ; 0 ;; 11 ; 2 ;; 12 ; 0 ;; 13 ; 2 ;; 14 ; 1 ;; 15 ; 24 ;; 16 ; 18 ;; 17 ; 12 ;; 18 ; 5 ;; 19 ; 4 ;; 20 ; 1 ;; 21 ; 2 ;; 22 ; 1 ;; 23 ; 4 ;; 24 ; 2 ;; 25 ; 4 ;; 26 ; 1 ;; 27 ; 1 ;; 28 ; 4 ;; 29 ; 5 ;; 30 ; 1 ;; 31 ; 0 ;; 32 ; 2 ;+----------------------------------------------+-------------------------------++---------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+-------------------------------+; Number of Signals Sourced Out (Average = 8.07) ; Number of LABs (Total = 148) ;+-------------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 30 ;; 2 ; 8 ;; 3 ; 5 ;; 4 ; 10 ;; 5 ; 5 ;; 6 ; 5 ;; 7 ; 2 ;; 8 ; 6 ;; 9 ; 9 ;; 10 ; 8 ;; 11 ; 10 ;; 12 ; 14 ;; 13 ; 8 ;; 14 ; 10 ;; 15 ; 6 ;; 16 ; 9 ;; 17 ; 1 ;; 18 ; 0 ;; 19 ; 0 ;; 20 ; 1 ;; 21 ; 0 ;; 22 ; 1 ;+-------------------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+-------------------------------+; Number of Distinct Inputs (Average = 11.52) ; Number of LABs (Total = 148) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 3 ;; 2 ; 18 ;; 3 ; 7 ;; 4 ; 12 ;; 5 ; 6 ;; 6 ; 11 ;; 7 ; 1 ;; 8 ; 4 ;; 9 ; 3 ;; 10 ; 0 ;; 11 ; 5 ;; 12 ; 3 ;; 13 ; 4 ;; 14 ; 12 ;; 15 ; 10 ;; 16 ; 9 ;; 17 ; 7 ;; 18 ; 11 ;; 19 ; 1 ;; 20 ; 4 ;; 21 ; 1 ;; 22 ; 1 ;; 23 ; 2 ;; 24 ; 3 ;; 25 ; 1 ;; 26 ; 0 ;; 27 ; 1 ;; 28 ; 5 ;; 29 ; 0 ;; 30 ; 1 ;; 31 ; 1 ;+----------------------------------------------+-------------------------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Active Serial ;; Error detection CRC ; Off ;; nCEO ; As output driving ground ;; ASDO,nCSO ; As input tri-stated ;; Reserve all unused pins ; As input tri-stated ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++------------------------------------------------------------+; Estimated Delay Added for Hold Timing ;+-----------------+----------------------+-------------------+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;+-----------------+----------------------+-------------------+; CLOCK_IN ; CLOCK_IN ; 1.19932 ;+-----------------+----------------------+-------------------+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.+----------------------------+; Advanced Data - General ;+--------------------+-------+; Name ; Value ;+--------------------+-------+; Status Code ; 0 ;; Desired User Slack ; 0 ;; Fit Attempts ; 1 ;+--------------------+-------++---------------------------------------------------------------------------------------+; Advanced Data - Placement Preparation ;+------------------------------------------------------------------+--------------------+; Name ; Value ;+------------------------------------------------------------------+--------------------+; Auto Fit Point 1 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 4 ;; Mid Slack - Fit Attempt 1 ; -52999 ;; Internal Atom Count - Fit Attempt 1 ; 1997 ;; LE/ALM Count - Fit Attempt 1 ; 1663 ;; LAB Count - Fit Attempt 1 ; 148 ;; Outputs per Lab - Fit Attempt 1 ; 8.068 ;; Inputs per LAB - Fit Attempt 1 ; 11.041 ;; Global Inputs per LAB - Fit Attempt 1 ; 0.432 ;; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:136;1:11;2:1 ;; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:95;1:35;2:10;3:8 ;; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:95;1:35;2:10;3:8 ;; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:148 ;; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:87;1:58;2:3 ;; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:101;1:46;2:1 ;; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:95;1:41;2:12 ;; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:86;1:42;2:20 ;; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:86;1:61;2:1 ;; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:127;1:21 ;; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:139;1:9 ;; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:134;1:14 ;; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:140;2:7 ;; LEs in Chains - Fit Attempt 1 ; 641 ;; LEs in Long Chains - Fit Attempt 1 ; 155 ;; LABs with Chains - Fit Attempt 1 ; 69 ;; LABs with Multiple Chains - Fit Attempt 1 ; 2 ;; Time - Fit Attempt 1 ; 0 ;; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;+------------------------------------------------------------------+--------------------++----------------------------------------------+; Advanced Data - Placement ;+-------------------------------------+--------+; Name ; Value ;+-------------------------------------+--------+; Auto Fit Point 2 - Fit Attempt 1 ; ff ;; Early Wire Use - Fit Attempt 1 ; 1 ;; Early Slack - Fit Attempt 1 ; -58133 ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 2 ;; Mid Slack - Fit Attempt 1 ; -52969 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 5 - Fit Attempt 1 ; ff ;; Mid Wire Use - Fit Attempt 1 ; 2 ;; Mid Slack - Fit Attempt 1 ; -51441 ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Auto Fit Point 6 - Fit Attempt 1 ; ff ;; Late Wire Use - Fit Attempt 1 ; 2 ;; Late Slack - Fit Attempt 1 ; -50848 ;; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;; Auto Fit Point 7 - Fit Attempt 1 ; ff ;; Time - Fit Attempt 1 ; 2 ;; Time in tsm_tan.dll - Fit Attempt 1 ; 0.188 ;+-------------------------------------+--------++---------------------------------------------------+; Advanced Data - Routing ;+-------------------------------------+-------------+; Name ; Value ;+-------------------------------------+-------------+; Early Slack - Fit Attempt 1 ; -43804 ;; Early Wire Use - Fit Attempt 1 ; 2 ;; Peak Regional Wire - Fit Attempt 1 ; 6 ;; Mid Slack - Fit Attempt 1 ; -45236 ;; Late Slack - Fit Attempt 1 ; -2147483648 ;; Late Wire Use - Fit Attempt 1 ; 2 ;; Time - Fit Attempt 1 ; 3 ;; Time in tsm_tan.dll - Fit Attempt 1 ; 0.969 ;+-------------------------------------+-------------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 9.0 Build 132 02/25/2009 SJ Web EditionInfo: Processing started: Tue May 11 23:49:37 2010Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off HD_ADPCM_Codec -c HD_ADPCM_CodecInfo: Selected device EP2C20F484C7 for design "HD_ADPCM_Codec"Info: Low junction temperature is 0 degrees CInfo: High junction temperature is 85 degrees CInfo: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning: Feature LogicLock is not available with your current licenseInfo: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo: Device EP2C15AF484C7 is compatibleInfo: Device EP2C35F484C7 is compatibleInfo: Device EP2C50F484C7 is compatibleInfo: Fitter converted 3 user pins into dedicated programming pinsInfo: Pin ~ASDO~ is reserved at location C4Info: Pin ~nCSO~ is reserved at location C3Info: Pin ~LVDS91p/nCEO~ is reserved at location W20Info: Fitter is using the Classic Timing AnalyzerInfo: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.Info: Automatically promoted node CLOCK_IN (placed in PIN D12 (CLK10, LVDSCLK5n, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11Info: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node I2S_Driver:u3|I2S_ClockInfo: Destination node Flash_Memory_Driver:u4|Flash_Memory_ClockInfo: Destination node I2S_ACTIVE_INInfo: Automatically promoted node Flash_Memory_Driver:u4|Flash_Memory_ClockInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node Flash_Memory_Driver:u4|Flash_Memory_Clock~1Info: Automatically promoted node I2S_Driver:u3|I2S_PCM_DATA_ACCESS_OUTInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Automatically promoted node I2S_Driver:u3|I2S_ClockInfo: Automatically promoted destinations to use location or clock signal Global ClockInfo: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node I2S_Driver:u3|I2S_PCM_DATA_ACCESS_OUTInfo: Destination node I2S_Driver:u3|I2S_Clock~1Info: Destination node I2S_CLOCK_OUTInfo: Starting register packingExtra Info: Performing register packing on registers with non-logic cell location assignmentsExtra Info: Completed register packing on registers with non-logic cell location assignmentsExtra Info: Started Fast Input/Output/OE register processingExtra Info: Finished Fast Input/Output/OE register processingExtra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and densityExtra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocksInfo: Finished register packingExtra Info: Packed 40 registers into blocks of type Embedded multiplier blockExtra Info: Created 40 register duplicatesInfo: Fitter preparation operations ending: elapsed time is 00:00:02Info: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time is 00:00:00Info: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Fitter placement operations ending: elapsed time is 00:00:02Info: Slack time is -48.815 ns between source register "ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]" and destination register "ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[0]"Info: + Largest register to register requirement is 0.768 nsInfo: Shortest clock path from clock "CLOCK_IN" to destination register is 2.608 nsInfo: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 4; CLK Node = 'CLOCK_IN'Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 325; COMB Node = 'CLOCK_IN~clkctrl'Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.608 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[0]'Info: Total cell delay = 1.385 ns ( 53.11 % )Info: Total interconnect delay = 1.223 ns ( 46.89 % )Info: Longest clock path from clock "CLOCK_IN" to destination register is 2.608 nsInfo: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 4; CLK Node = 'CLOCK_IN'Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 325; COMB Node = 'CLOCK_IN~clkctrl'Info: 3: + IC(0.988 ns) + CELL(0.602 ns) = 2.608 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[0]'Info: Total cell delay = 1.385 ns ( 53.11 % )Info: Total interconnect delay = 1.223 ns ( 46.89 % )Info: Shortest clock path from clock "CLOCK_IN" to source register is 2.878 nsInfo: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 4; CLK Node = 'CLOCK_IN'Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 325; COMB Node = 'CLOCK_IN~clkctrl'Info: 3: + IC(0.988 ns) + CELL(0.872 ns) = 2.878 ns; Loc. = Unassigned; Fanout = 11; REG Node = 'ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]'Info: Total cell delay = 1.655 ns ( 57.51 % )Info: Total interconnect delay = 1.223 ns ( 42.49 % )Info: Longest clock path from clock "CLOCK_IN" to source register is 2.878 nsInfo: 1: + IC(0.000 ns) + CELL(0.783 ns) = 0.783 ns; Loc. = Unassigned; Fanout = 4; CLK Node = 'CLOCK_IN'Info: 2: + IC(0.235 ns) + CELL(0.000 ns) = 1.018 ns; Loc. = Unassigned; Fanout = 325; COMB Node = 'CLOCK_IN~clkctrl'Info: 3: + IC(0.988 ns) + CELL(0.872 ns) = 2.878 ns; Loc. = Unassigned; Fanout = 11; REG Node = 'ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]'Info: Total cell delay = 1.655 ns ( 57.51 % )Info: Total interconnect delay = 1.223 ns ( 42.49 % )Info: Micro clock to output delay of source is 0.000 nsInfo: Micro setup delay of destination is -0.038 nsInfo: - Longest register to register delay is 49.583 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 11; REG Node = 'ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]'Info: 2: + IC(0.000 ns) + CELL(3.257 ns) = 3.257 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1~DATAOUT15'Info: 3: + IC(0.000 ns) + CELL(0.304 ns) = 3.561 ns; Loc. = Unassigned; Fanout = 4; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_out2~DATAOUT15'Info: 4: + IC(0.965 ns) + CELL(0.517 ns) = 5.043 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[2]~1'Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 5.123 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[3]~3'Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 5.203 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[4]~5'Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 5.283 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[5]~7'Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 5.363 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[6]~9'Info: 9: + IC(0.000 ns) + CELL(0.458 ns) = 5.821 ns; Loc. = Unassigned; Fanout = 19; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[7]~10'Info: 10: + IC(1.073 ns) + CELL(0.177 ns) = 7.071 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[50]~221'Info: 11: + IC(1.073 ns) + CELL(0.495 ns) = 8.639 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[3]~3'Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 8.719 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[4]~5'Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 8.799 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[5]~7'Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 8.879 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[6]~9'Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 8.959 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[7]~11'Info: 16: + IC(0.000 ns) + CELL(0.458 ns) = 9.417 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[8]~12'Info: 17: + IC(0.388 ns) + CELL(0.521 ns) = 10.326 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[58]~197'Info: 18: + IC(1.015 ns) + CELL(0.517 ns) = 11.858 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[3]~3'Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 11.938 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[4]~5'Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 12.018 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[5]~7'Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 12.098 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[6]~9'Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 12.178 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[7]~11'Info: 23: + IC(0.000 ns) + CELL(0.458 ns) = 12.636 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[8]~12'Info: 24: + IC(1.039 ns) + CELL(0.178 ns) = 13.853 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[67]~581'Info: 25: + IC(1.375 ns) + CELL(0.517 ns) = 15.745 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[4]~5'Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 15.825 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[5]~7'Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 15.905 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[6]~9'Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 15.985 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[7]~11'Info: 29: + IC(0.000 ns) + CELL(0.458 ns) = 16.443 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[8]~12'Info: 30: + IC(1.039 ns) + CELL(0.177 ns) = 17.659 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[73]~174'Info: 31: + IC(0.498 ns) + CELL(0.495 ns) = 18.652 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[2]~1'Info: 32: + IC(0.000 ns) + CELL(0.080 ns) = 18.732 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[3]~3'Info: 33: + IC(0.000 ns) + CELL(0.080 ns) = 18.812 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[4]~5'Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 18.892 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[5]~7'Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 18.972 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[6]~9'Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 19.052 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[7]~11'Info: 37: + IC(0.000 ns) + CELL(0.458 ns) = 19.510 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[8]~12'Info: 38: + IC(0.588 ns) + CELL(0.319 ns) = 20.417 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[83]~544'Info: 39: + IC(1.016 ns) + CELL(0.517 ns) = 21.950 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[4]~5'Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 22.030 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[5]~7'Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 22.110 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[6]~9'Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 22.190 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[7]~11'Info: 43: + IC(0.000 ns) + CELL(0.458 ns) = 22.648 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[8]~12'Info: 44: + IC(0.895 ns) + CELL(0.319 ns) = 23.862 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[92]~547'Info: 45: + IC(1.017 ns) + CELL(0.517 ns) = 25.396 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[5]~7'Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 25.476 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[6]~9'Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 25.556 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[7]~11'Info: 48: + IC(0.000 ns) + CELL(0.458 ns) = 26.014 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[8]~12'Info: 49: + IC(0.896 ns) + CELL(0.319 ns) = 27.229 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[101]~550'Info: 50: + IC(1.359 ns) + CELL(0.517 ns) = 29.105 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[6]~9'Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 29.185 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[7]~11'Info: 52: + IC(0.000 ns) + CELL(0.458 ns) = 29.643 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[8]~12'Info: 53: + IC(1.238 ns) + CELL(0.319 ns) = 31.200 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[110]~553'Info: 54: + IC(1.362 ns) + CELL(0.517 ns) = 33.079 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_14_result_int[7]~11'Info: 55: + IC(0.000 ns) + CELL(0.458 ns) = 33.537 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_14_result_int[8]~12'Info: 56: + IC(0.498 ns) + CELL(0.177 ns) = 34.212 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[113]~94'Info: 57: + IC(1.073 ns) + CELL(0.495 ns) = 35.780 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[2]~1'Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 35.860 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[3]~3'Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 35.940 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[4]~5'Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 36.020 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[5]~7'Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 36.100 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[6]~9'Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 36.180 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[7]~11'Info: 63: + IC(0.000 ns) + CELL(0.458 ns) = 36.638 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[8]~12'Info: 64: + IC(0.598 ns) + CELL(0.319 ns) = 37.555 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[124]~563'Info: 65: + IC(1.016 ns) + CELL(0.517 ns) = 39.088 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[5]~7'Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 39.168 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[6]~9'Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 39.248 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[7]~11'Info: 68: + IC(0.000 ns) + CELL(0.458 ns) = 39.706 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[8]~12'Info: 69: + IC(0.949 ns) + CELL(0.319 ns) = 40.974 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[132]~567'Info: 70: + IC(1.070 ns) + CELL(0.517 ns) = 42.561 ns; Loc. = Unassigned; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[5]~7'Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 42.641 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[6]~9'Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 42.721 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[7]~11'Info: 73: + IC(0.000 ns) + CELL(0.458 ns) = 43.179 ns; Loc. = Unassigned; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[8]~12'Info: 74: + IC(0.895 ns) + CELL(0.319 ns) = 44.393 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[142]~569'Info: 75: + IC(1.359 ns) + CELL(0.517 ns) = 46.269 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|op_9~32'Info: 76: + IC(0.000 ns) + CELL(0.458 ns) = 46.727 ns; Loc. = Unassigned; Fanout = 13; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|op_9~33'Info: 77: + IC(0.732 ns) + CELL(0.177 ns) = 47.636 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[145]~30'Info: 78: + IC(0.498 ns) + CELL(0.495 ns) = 48.629 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[2]~1'Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 48.709 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[3]~3'Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 48.789 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[4]~5'Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 48.869 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[5]~7'Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 48.949 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[6]~9'Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 49.029 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[7]~11'Info: 84: + IC(0.000 ns) + CELL(0.458 ns) = 49.487 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[8]~12'Info: 85: + IC(0.000 ns) + CELL(0.096 ns) = 49.583 ns; Loc. = Unassigned; Fanout = 1; REG Node = 'ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[0]'Info: Total cell delay = 24.059 ns ( 48.52 % )Info: Total interconnect delay = 25.524 ns ( 51.48 % )Info: Estimated most critical path is register to register delay of 49.583 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = DSPMULT_X28_Y17_N0; Fanout = 11; REG Node = 'ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[9]'Info: 2: + IC(0.000 ns) + CELL(3.257 ns) = 3.257 ns; Loc. = DSPMULT_X28_Y17_N0; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_mult1~DATAOUT15'Info: 3: + IC(0.000 ns) + CELL(0.304 ns) = 3.561 ns; Loc. = DSPOUT_X28_Y17_N2; Fanout = 4; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated|mac_out2~DATAOUT15'Info: 4: + IC(0.965 ns) + CELL(0.517 ns) = 5.043 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[2]~1'Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 5.123 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[3]~3'Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 5.203 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[4]~5'Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 5.283 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[5]~7'Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 5.363 ns; Loc. = LAB_X30_Y17; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[6]~9'Info: 9: + IC(0.000 ns) + CELL(0.458 ns) = 5.821 ns; Loc. = LAB_X30_Y17; Fanout = 19; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_6_result_int[7]~10'Info: 10: + IC(1.073 ns) + CELL(0.177 ns) = 7.071 ns; Loc. = LAB_X29_Y18; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[50]~221'Info: 11: + IC(1.073 ns) + CELL(0.495 ns) = 8.639 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[3]~3'Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 8.719 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[4]~5'Info: 13: + IC(0.000 ns) + CELL(0.080 ns) = 8.799 ns; Loc. = LAB_X30_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[5]~7'Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 8.879 ns; Loc. = LAB_X30_Y17; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[6]~9'Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 8.959 ns; Loc. = LAB_X30_Y17; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[7]~11'Info: 16: + IC(0.000 ns) + CELL(0.458 ns) = 9.417 ns; Loc. = LAB_X30_Y17; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_7_result_int[8]~12'Info: 17: + IC(0.388 ns) + CELL(0.521 ns) = 10.326 ns; Loc. = LAB_X29_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[58]~197'Info: 18: + IC(1.015 ns) + CELL(0.517 ns) = 11.858 ns; Loc. = LAB_X31_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[3]~3'Info: 19: + IC(0.000 ns) + CELL(0.080 ns) = 11.938 ns; Loc. = LAB_X31_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[4]~5'Info: 20: + IC(0.000 ns) + CELL(0.080 ns) = 12.018 ns; Loc. = LAB_X31_Y17; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[5]~7'Info: 21: + IC(0.000 ns) + CELL(0.080 ns) = 12.098 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[6]~9'Info: 22: + IC(0.000 ns) + CELL(0.080 ns) = 12.178 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[7]~11'Info: 23: + IC(0.000 ns) + CELL(0.458 ns) = 12.636 ns; Loc. = LAB_X31_Y17; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_8_result_int[8]~12'Info: 24: + IC(1.039 ns) + CELL(0.178 ns) = 13.853 ns; Loc. = LAB_X29_Y17; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[67]~581'Info: 25: + IC(1.375 ns) + CELL(0.517 ns) = 15.745 ns; Loc. = LAB_X32_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[4]~5'Info: 26: + IC(0.000 ns) + CELL(0.080 ns) = 15.825 ns; Loc. = LAB_X32_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[5]~7'Info: 27: + IC(0.000 ns) + CELL(0.080 ns) = 15.905 ns; Loc. = LAB_X32_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[6]~9'Info: 28: + IC(0.000 ns) + CELL(0.080 ns) = 15.985 ns; Loc. = LAB_X32_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[7]~11'Info: 29: + IC(0.000 ns) + CELL(0.458 ns) = 16.443 ns; Loc. = LAB_X32_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_9_result_int[8]~12'Info: 30: + IC(1.039 ns) + CELL(0.177 ns) = 17.659 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[73]~174'Info: 31: + IC(0.498 ns) + CELL(0.495 ns) = 18.652 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[2]~1'Info: 32: + IC(0.000 ns) + CELL(0.080 ns) = 18.732 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[3]~3'Info: 33: + IC(0.000 ns) + CELL(0.080 ns) = 18.812 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[4]~5'Info: 34: + IC(0.000 ns) + CELL(0.080 ns) = 18.892 ns; Loc. = LAB_X34_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[5]~7'Info: 35: + IC(0.000 ns) + CELL(0.080 ns) = 18.972 ns; Loc. = LAB_X34_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[6]~9'Info: 36: + IC(0.000 ns) + CELL(0.080 ns) = 19.052 ns; Loc. = LAB_X34_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[7]~11'Info: 37: + IC(0.000 ns) + CELL(0.458 ns) = 19.510 ns; Loc. = LAB_X34_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_10_result_int[8]~12'Info: 38: + IC(0.588 ns) + CELL(0.319 ns) = 20.417 ns; Loc. = LAB_X33_Y20; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[83]~544'Info: 39: + IC(1.016 ns) + CELL(0.517 ns) = 21.950 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[4]~5'Info: 40: + IC(0.000 ns) + CELL(0.080 ns) = 22.030 ns; Loc. = LAB_X35_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[5]~7'Info: 41: + IC(0.000 ns) + CELL(0.080 ns) = 22.110 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[6]~9'Info: 42: + IC(0.000 ns) + CELL(0.080 ns) = 22.190 ns; Loc. = LAB_X35_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[7]~11'Info: 43: + IC(0.000 ns) + CELL(0.458 ns) = 22.648 ns; Loc. = LAB_X35_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_11_result_int[8]~12'Info: 44: + IC(0.895 ns) + CELL(0.319 ns) = 23.862 ns; Loc. = LAB_X33_Y20; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[92]~547'Info: 45: + IC(1.017 ns) + CELL(0.517 ns) = 25.396 ns; Loc. = LAB_X36_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[5]~7'Info: 46: + IC(0.000 ns) + CELL(0.080 ns) = 25.476 ns; Loc. = LAB_X36_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[6]~9'Info: 47: + IC(0.000 ns) + CELL(0.080 ns) = 25.556 ns; Loc. = LAB_X36_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[7]~11'Info: 48: + IC(0.000 ns) + CELL(0.458 ns) = 26.014 ns; Loc. = LAB_X36_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_12_result_int[8]~12'Info: 49: + IC(0.896 ns) + CELL(0.319 ns) = 27.229 ns; Loc. = LAB_X33_Y20; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[101]~550'Info: 50: + IC(1.359 ns) + CELL(0.517 ns) = 29.105 ns; Loc. = LAB_X36_Y21; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[6]~9'Info: 51: + IC(0.000 ns) + CELL(0.080 ns) = 29.185 ns; Loc. = LAB_X36_Y21; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[7]~11'Info: 52: + IC(0.000 ns) + CELL(0.458 ns) = 29.643 ns; Loc. = LAB_X36_Y21; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_13_result_int[8]~12'Info: 53: + IC(1.238 ns) + CELL(0.319 ns) = 31.200 ns; Loc. = LAB_X33_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[110]~553'Info: 54: + IC(1.362 ns) + CELL(0.517 ns) = 33.079 ns; Loc. = LAB_X37_Y21; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_14_result_int[7]~11'Info: 55: + IC(0.000 ns) + CELL(0.458 ns) = 33.537 ns; Loc. = LAB_X37_Y21; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_14_result_int[8]~12'Info: 56: + IC(0.498 ns) + CELL(0.177 ns) = 34.212 ns; Loc. = LAB_X37_Y21; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[113]~94'Info: 57: + IC(1.073 ns) + CELL(0.495 ns) = 35.780 ns; Loc. = LAB_X38_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[2]~1'Info: 58: + IC(0.000 ns) + CELL(0.080 ns) = 35.860 ns; Loc. = LAB_X38_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[3]~3'Info: 59: + IC(0.000 ns) + CELL(0.080 ns) = 35.940 ns; Loc. = LAB_X38_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[4]~5'Info: 60: + IC(0.000 ns) + CELL(0.080 ns) = 36.020 ns; Loc. = LAB_X38_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[5]~7'Info: 61: + IC(0.000 ns) + CELL(0.080 ns) = 36.100 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[6]~9'Info: 62: + IC(0.000 ns) + CELL(0.080 ns) = 36.180 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[7]~11'Info: 63: + IC(0.000 ns) + CELL(0.458 ns) = 36.638 ns; Loc. = LAB_X38_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_15_result_int[8]~12'Info: 64: + IC(0.598 ns) + CELL(0.319 ns) = 37.555 ns; Loc. = LAB_X37_Y20; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[124]~563'Info: 65: + IC(1.016 ns) + CELL(0.517 ns) = 39.088 ns; Loc. = LAB_X39_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[5]~7'Info: 66: + IC(0.000 ns) + CELL(0.080 ns) = 39.168 ns; Loc. = LAB_X39_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[6]~9'Info: 67: + IC(0.000 ns) + CELL(0.080 ns) = 39.248 ns; Loc. = LAB_X39_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[7]~11'Info: 68: + IC(0.000 ns) + CELL(0.458 ns) = 39.706 ns; Loc. = LAB_X39_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_16_result_int[8]~12'Info: 69: + IC(0.949 ns) + CELL(0.319 ns) = 40.974 ns; Loc. = LAB_X39_Y18; Fanout = 3; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[132]~567'Info: 70: + IC(1.070 ns) + CELL(0.517 ns) = 42.561 ns; Loc. = LAB_X40_Y20; Fanout = 2; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[5]~7'Info: 71: + IC(0.000 ns) + CELL(0.080 ns) = 42.641 ns; Loc. = LAB_X40_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[6]~9'Info: 72: + IC(0.000 ns) + CELL(0.080 ns) = 42.721 ns; Loc. = LAB_X40_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[7]~11'Info: 73: + IC(0.000 ns) + CELL(0.458 ns) = 43.179 ns; Loc. = LAB_X40_Y20; Fanout = 20; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_17_result_int[8]~12'Info: 74: + IC(0.895 ns) + CELL(0.319 ns) = 44.393 ns; Loc. = LAB_X37_Y20; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[142]~569'Info: 75: + IC(1.359 ns) + CELL(0.517 ns) = 46.269 ns; Loc. = LAB_X40_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|op_9~32'Info: 76: + IC(0.000 ns) + CELL(0.458 ns) = 46.727 ns; Loc. = LAB_X40_Y19; Fanout = 13; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|op_9~33'Info: 77: + IC(0.732 ns) + CELL(0.177 ns) = 47.636 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|StageOut[145]~30'Info: 78: + IC(0.498 ns) + CELL(0.495 ns) = 48.629 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[2]~1'Info: 79: + IC(0.000 ns) + CELL(0.080 ns) = 48.709 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[3]~3'Info: 80: + IC(0.000 ns) + CELL(0.080 ns) = 48.789 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[4]~5'Info: 81: + IC(0.000 ns) + CELL(0.080 ns) = 48.869 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[5]~7'Info: 82: + IC(0.000 ns) + CELL(0.080 ns) = 48.949 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[6]~9'Info: 83: + IC(0.000 ns) + CELL(0.080 ns) = 49.029 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[7]~11'Info: 84: + IC(0.000 ns) + CELL(0.458 ns) = 49.487 ns; Loc. = LAB_X39_Y19; Fanout = 1; COMB Node = 'ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider|add_sub_19_result_int[8]~12'Info: 85: + IC(0.000 ns) + CELL(0.096 ns) = 49.583 ns; Loc. = LAB_X39_Y19; Fanout = 1; REG Node = 'ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[0]'Info: Total cell delay = 24.059 ns ( 48.52 % )Info: Total interconnect delay = 25.524 ns ( 51.48 % )Info: Fitter routing operations beginningInfo: Average interconnect usage is 1% of the available device resourcesInfo: Peak interconnect usage is 5% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27Info: Fitter routing operations ending: elapsed time is 00:00:03Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info: Optimizations that may affect the design's routability were skippedInfo: Optimizations that may affect the design's timing were skippedInfo: Started post-fitting delay annotationWarning: Found 78 output pins without output pin load capacitance assignmentInfo: Pin "I2C_DATA_INOUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2S_DATA_INOUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_DATA_INOUT[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_1_OUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_2_OUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_3_OUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_SEVEN_SEGMENT_4_OUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "S_RED_LEDS_OUT[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2C_CLOCK_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2S_LEFT_RIGHT_CLOCK_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2S_CLOCK_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "I2S_CORE_CLOCK_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_ADDRESS_OUT[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_nWE_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_nOE_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_nRESET_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "FLASH_MEMORY_nCE_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyWarning: Following 10 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting resultsInfo: Pin I2C_DATA_INOUT has a permanently enabled output enableInfo: Pin I2S_DATA_INOUT has a permanently enabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[0] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[1] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[2] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[3] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[4] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[5] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[6] has a permanently disabled output enableInfo: Pin FLASH_MEMORY_DATA_INOUT[7] has a permanently disabled output enableWarning: Following 38 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting resultsInfo: Pin FLASH_MEMORY_DATA_INOUT[0] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[1] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[2] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[3] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[4] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[5] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[6] has VCC driving its datain portInfo: Pin FLASH_MEMORY_DATA_INOUT[7] has VCC driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[0] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[1] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[2] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[3] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[4] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[5] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_1_OUT[6] has VCC driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[0] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[1] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[2] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[3] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[4] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[5] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_2_OUT[6] has VCC driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[0] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[1] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[2] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[3] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[4] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[5] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_3_OUT[6] has VCC driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[0] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[1] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[2] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[3] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[4] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[5] has GND driving its datain portInfo: Pin S_SEVEN_SEGMENT_4_OUT[6] has VCC driving its datain portInfo: Pin FLASH_MEMORY_nWE_OUT has VCC driving its datain portInfo: Pin FLASH_MEMORY_nRESET_OUT has VCC driving its datain portInfo: Quartus II Fitter was successful. 0 errors, 4 warningsInfo: Peak virtual memory: 211 megabytesInfo: Processing ended: Tue May 11 23:49:54 2010Info: Elapsed time: 00:00:17Info: Total CPU time (on all processors): 00:00:17