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[/] [audio/] [trunk/] [HD_ADPCM/] [HD_ADPCM_1Bit_Stereo_Decoder/] [HD_ADPCM_Codec.map.rpt] - Rev 6
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Analysis & Synthesis report for HD_ADPCM_CodecTue May 11 23:49:36 2010Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Analysis & Synthesis Summary3. Analysis & Synthesis Settings4. Analysis & Synthesis Source Files Read5. Analysis & Synthesis Resource Usage Summary6. Analysis & Synthesis Resource Utilization by Entity7. Analysis & Synthesis DSP Block Usage Summary8. Registers Removed During Synthesis9. General Register Statistics10. Inverted Register Statistics11. Multiplexer Restructuring Statistics (Restructuring Performed)12. Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult013. Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u5|lpm_divide:Div014. Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult015. Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u6|lpm_divide:Div016. lpm_mult Parameter Settings by Entity Instance17. Port Connectivity Checks: "Flash_Memory_Driver:u4"18. Port Connectivity Checks: "I2C_Driver:u2"19. Port Connectivity Checks: "SevenSegments_Driver:u0"20. Analysis & Synthesis Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2009 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+------------------------------------------------------------------------------+; Analysis & Synthesis Summary ;+------------------------------------+-----------------------------------------+; Analysis & Synthesis Status ; Successful - Tue May 11 23:49:36 2010 ;; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Web Edition ;; Revision Name ; HD_ADPCM_Codec ;; Top-level Entity Name ; HD_ADPCM_Codec ;; Family ; Cyclone II ;; Total logic elements ; 1,667 ;; Total combinational functions ; 1,633 ;; Dedicated logic registers ; 364 ;; Total registers ; 364 ;; Total pins ; 82 ;; Total virtual pins ; 0 ;; Total memory bits ; 0 ;; Embedded Multiplier 9-bit elements ; 4 ;; Total PLLs ; 0 ;+------------------------------------+-----------------------------------------++----------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Settings ;+----------------------------------------------------------------+--------------------+--------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------+--------------------+--------------------+; Device ; EP2C20F484C7 ; ;; Top-level entity name ; HD_ADPCM_Codec ; HD_ADPCM_Codec ;; Family name ; Cyclone II ; Stratix II ;; Optimization Technique ; Area ; Balanced ;; Use Generated Physical Constraints File ; Off ; ;; Use smart compilation ; Off ; Off ;; Restructure Multiplexers ; Auto ; Auto ;; Create Debugging Nodes for IP Cores ; Off ; Off ;; Preserve fewer node names ; On ; On ;; Disable OpenCore Plus hardware evaluation ; Off ; Off ;; Verilog Version ; Verilog_2001 ; Verilog_2001 ;; VHDL Version ; VHDL93 ; VHDL93 ;; State Machine Processing ; Auto ; Auto ;; Safe State Machine ; Off ; Off ;; Extract Verilog State Machines ; On ; On ;; Extract VHDL State Machines ; On ; On ;; Ignore Verilog initial constructs ; Off ; Off ;; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;; Add Pass-Through Logic to Inferred RAMs ; On ; On ;; Parallel Synthesis ; Off ; Off ;; DSP Block Balancing ; Auto ; Auto ;; NOT Gate Push-Back ; On ; On ;; Power-Up Don't Care ; On ; On ;; Remove Redundant Logic Cells ; Off ; Off ;; Remove Duplicate Registers ; On ; On ;; Ignore CARRY Buffers ; Off ; Off ;; Ignore CASCADE Buffers ; Off ; Off ;; Ignore GLOBAL Buffers ; Off ; Off ;; Ignore ROW GLOBAL Buffers ; Off ; Off ;; Ignore LCELL Buffers ; Off ; Off ;; Ignore SOFT Buffers ; On ; On ;; Limit AHDL Integers to 32 Bits ; Off ; Off ;; Carry Chain Length ; 70 ; 70 ;; Auto Carry Chains ; On ; On ;; Auto Open-Drain Pins ; On ; On ;; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;; Auto ROM Replacement ; On ; On ;; Auto RAM Replacement ; On ; On ;; Auto Shift Register Replacement ; Auto ; Auto ;; Auto Clock Enable Replacement ; On ; On ;; Strict RAM Replacement ; Off ; Off ;; Allow Synchronous Control Signals ; On ; On ;; Force Use of Synchronous Clear Signals ; Off ; Off ;; Auto RAM to Logic Cell Conversion ; Off ; Off ;; Auto Resource Sharing ; Off ; Off ;; Allow Any RAM Size For Recognition ; Off ; Off ;; Allow Any ROM Size For Recognition ; Off ; Off ;; Allow Any Shift Register Size For Recognition ; Off ; Off ;; Use LogicLock Constraints during Resource Balancing ; On ; On ;; Ignore translate_off and synthesis_off directives ; Off ; Off ;; Timing-Driven Synthesis ; Off ; Off ;; Show Parameter Settings Tables in Synthesis Report ; On ; On ;; Ignore Maximum Fan-Out Assignments ; Off ; Off ;; Synchronization Register Chain Length ; 2 ; 2 ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; HDL message level ; Level2 ; Level2 ;; Suppress Register Optimization Related Messages ; Off ; Off ;; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;; Clock MUX Protection ; On ; On ;; Auto Gated Clock Conversion ; Off ; Off ;; Block Design Naming ; Auto ; Auto ;; SDC constraint protection ; Off ; Off ;; Synthesis Effort ; Auto ; Auto ;; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;; Analysis & Synthesis Message Level ; Medium ; Medium ;+----------------------------------------------------------------+--------------------+--------------------++---------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Source Files Read ;+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+; HD_ADPCM_Codec.vhd ; yes ; User VHDL File ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/HD_ADPCM_Codec.vhd ;; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/lpm_mult.tdf ;; aglobal90.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/aglobal90.inc ;; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/lpm_add_sub.inc ;; multcore.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/multcore.inc ;; bypassff.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/bypassff.inc ;; altshift.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/altshift.inc ;; db/mult_pu01.tdf ; yes ; Auto-Generated Megafunction ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/db/mult_pu01.tdf ;; lpm_divide.tdf ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/lpm_divide.tdf ;; abs_divider.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/abs_divider.inc ;; sign_div_unsign.inc ; yes ; Megafunction ; c:/altera/90/quartus/libraries/megafunctions/sign_div_unsign.inc ;; db/lpm_divide_aem.tdf ; yes ; Auto-Generated Megafunction ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/db/lpm_divide_aem.tdf ;; db/sign_div_unsign_klh.tdf ; yes ; Auto-Generated Megafunction ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/db/sign_div_unsign_klh.tdf ;; db/alt_u_div_e2f.tdf ; yes ; Auto-Generated Megafunction ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/db/alt_u_div_e2f.tdf ;; db/add_sub_lkc.tdf ; yes ; Auto-Generated Megafunction ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/db/add_sub_lkc.tdf ;; db/add_sub_mkc.tdf ; yes ; Auto-Generated Megafunction ; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/db/add_sub_mkc.tdf ;+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------++--------------------------------------------------------+; Analysis & Synthesis Resource Usage Summary ;+---------------------------------------------+----------+; Resource ; Usage ;+---------------------------------------------+----------+; Estimated Total logic elements ; 1,667 ;; ; ;; Total combinational functions ; 1633 ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 384 ;; -- 3 input functions ; 307 ;; -- <=2 input functions ; 942 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 1056 ;; -- arithmetic mode ; 577 ;; ; ;; Total registers ; 364 ;; -- Dedicated logic registers ; 364 ;; -- I/O registers ; 0 ;; ; ;; I/O pins ; 82 ;; Embedded Multiplier 9-bit elements ; 4 ;; Maximum fan-out node ; CLOCK_IN ;; Maximum fan-out ; 288 ;; Total fan-out ; 5407 ;; Average fan-out ; 2.60 ;+---------------------------------------------+----------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Resource Utilization by Entity ;+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+; |HD_ADPCM_Codec ; 1633 (112) ; 364 (82) ; 0 ; 4 ; 0 ; 2 ; 82 ; 0 ; |HD_ADPCM_Codec ; work ;; |ADPCM_Decoder_1_Bit:u5| ; 668 (379) ; 74 (74) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5 ; work ;; |lpm_divide:Div0| ; 289 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0 ; work ;; |lpm_divide_aem:auto_generated| ; 289 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated ; work ;; |sign_div_unsign_klh:divider| ; 289 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider ; work ;; |alt_u_div_e2f:divider| ; 289 (289) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider ; work ;; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0 ; work ;; |mult_pu01:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0|mult_pu01:auto_generated ; work ;; |ADPCM_Decoder_1_Bit:u6| ; 659 (370) ; 77 (77) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6 ; work ;; |lpm_divide:Div0| ; 289 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0 ; work ;; |lpm_divide_aem:auto_generated| ; 289 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated ; work ;; |sign_div_unsign_klh:divider| ; 289 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider ; work ;; |alt_u_div_e2f:divider| ; 289 (289) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0|lpm_divide_aem:auto_generated|sign_div_unsign_klh:divider|alt_u_div_e2f:divider ; work ;; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0 ; work ;; |mult_pu01:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0|mult_pu01:auto_generated ; work ;; |Flash_Memory_Driver:u4| ; 41 (41) ; 61 (61) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|Flash_Memory_Driver:u4 ; work ;; |I2C_Driver:u2| ; 72 (72) ; 34 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|I2C_Driver:u2 ; work ;; |I2S_Driver:u3| ; 72 (72) ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|I2S_Driver:u3 ; work ;; |LEDs_Bar_Driver:u1| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |HD_ADPCM_Codec|LEDs_Bar_Driver:u1 ; work ;+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-----------------------------------------------------+; Analysis & Synthesis DSP Block Usage Summary ;+---------------------------------------+-------------+; Statistic ; Number Used ;+---------------------------------------+-------------+; Simple Multipliers (9-bit) ; 0 ;; Simple Multipliers (18-bit) ; 2 ;; Embedded Multiplier Blocks ; -- ;; Embedded Multiplier 9-bit elements ; 4 ;; Signed Embedded Multipliers ; 0 ;; Unsigned Embedded Multipliers ; 2 ;; Mixed Sign Embedded Multipliers ; 0 ;; Variable Sign Embedded Multipliers ; 0 ;; Dedicated Input Shift Register Chains ; 0 ;+---------------------------------------+-------------+Note: number of Embedded Multiplier Blocks used is only available after a successful fit.+---------------------------------------------------------------------------------------------------------------------------+; Registers Removed During Synthesis ;+-------------------------------------------------------+-------------------------------------------------------------------+; Register name ; Reason for Removal ;+-------------------------------------------------------+-------------------------------------------------------------------+; ADPCM_Bit_Counter[0] ; Stuck at GND due to stuck port data_in ;; ADPCM_Decoder_1_Bit:u5|Active_Module ; Merged with ADPCM_Decoder_1_Bit:u6|Active_Module ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_State_Counter[0] ; Merged with ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_State_Counter[0] ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_State_Counter[1] ; Merged with ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_State_Counter[1] ;; ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_State_Counter[2] ; Merged with ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_State_Counter[2] ;; Flash_Memory_Driver:u4|FLASH_MEMORY_nRESET ; Merged with Flash_Memory_Driver:u4|FLASH_MEMORY_nWE ;; I2C_REGISTER_ADDRESS[5..7] ; Stuck at GND due to stuck port data_in ;; Flash_Memory_Driver:u4|FLASH_MEMORY_nWE ; Stuck at VCC due to stuck port data_in ;; ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[16] ; Lost fanout ;; ADPCM_Decoder_1_Bit:u5|Last_PCM_Data[16] ; Lost fanout ;; ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[16] ; Lost fanout ;; ADPCM_Decoder_1_Bit:u6|Last_PCM_Data[16] ; Lost fanout ;; ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[14] ; Stuck at GND due to stuck port data_in ;; ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[14] ; Stuck at GND due to stuck port data_in ;; ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[15] ; Merged with ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[15] ;; Total Number of Removed Registers = 17 ; ;+-------------------------------------------------------+-------------------------------------------------------------------++------------------------------------------------------+; General Register Statistics ;+----------------------------------------------+-------+; Statistic ; Value ;+----------------------------------------------+-------+; Total registers ; 364 ;; Number of registers using Synchronous Clear ; 107 ;; Number of registers using Synchronous Load ; 30 ;; Number of registers using Asynchronous Clear ; 1 ;; Number of registers using Asynchronous Load ; 0 ;; Number of registers using Clock Enable ; 227 ;; Number of registers using Preset ; 0 ;+----------------------------------------------+-------++----------------------------------------------------------+; Inverted Register Statistics ;+------------------------------------------------+---------+; Inverted Register ; Fan out ;+------------------------------------------------+---------+; ADPCM_Bit_Counter[1] ; 7 ;; ADPCM_Bit_Counter[2] ; 6 ;; ADPCM_Decoder_1_Bit:u5|Last_PCM_Data[15] ; 2 ;; ADPCM_Decoder_1_Bit:u5|Last_PCM_Data[0] ; 2 ;; I2C_REGISTER_ADDRESS[4] ; 2 ;; I2C_REGISTER_ADDRESS[1] ; 1 ;; I2C_REGISTER_DATA[0] ; 2 ;; ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[15] ; 2 ;; ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[0] ; 1 ;; AUDIO_CODEC_VOLUME[5] ; 4 ;; AUDIO_CODEC_VOLUME[6] ; 4 ;; AUDIO_CODEC_VOLUME[4] ; 4 ;; ADPCM_Decoder_1_Bit:u6|Last_PCM_Data[0] ; 2 ;; ADPCM_Decoder_1_Bit:u6|Last_PCM_Data[15] ; 2 ;; ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[0] ; 1 ;; Total number of inverted registers = 15 ; ;+------------------------------------------------+---------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Restructuring Statistics (Restructuring Performed) ;+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------+; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |HD_ADPCM_Codec|ADPCM_DECODER_DATA_LEFT ;; 6:1 ; 22 bits ; 88 LEs ; 0 LEs ; 88 LEs ; Yes ; |HD_ADPCM_Codec|Flash_Memory_Driver:u4|FLASH_MEMORY_ADDRESS[14] ;; 8:1 ; 6 bits ; 30 LEs ; 24 LEs ; 6 LEs ; Yes ; |HD_ADPCM_Codec|I2C_REGISTER_DATA[6] ;; 4:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |HD_ADPCM_Codec|AUDIO_CODEC_VOLUME[2] ;; 4:1 ; 10 bits ; 20 LEs ; 0 LEs ; 20 LEs ; Yes ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|ADPCM_Decoder_Step_Size_Table_Pointer[9] ;; 4:1 ; 10 bits ; 20 LEs ; 0 LEs ; 20 LEs ; Yes ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|ADPCM_Decoder_Step_Size_Table_Pointer[4] ;; 9:1 ; 15 bits ; 90 LEs ; 30 LEs ; 60 LEs ; Yes ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5|PCM_Data[9] ;; 9:1 ; 15 bits ; 90 LEs ; 30 LEs ; 60 LEs ; Yes ; |HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6|PCM_Data[1] ;; 4:1 ; 3 bits ; 6 LEs ; 0 LEs ; 6 LEs ; Yes ; |HD_ADPCM_Codec|AUDIO_CODEC_VOLUME[4] ;+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------++----------------------------------------------------------------------------------------+; Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0 ;+------------------------------------------------+------------+--------------------------+; Parameter Name ; Value ; Type ;+------------------------------------------------+------------+--------------------------+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; LPM_WIDTHA ; 10 ; Untyped ;; LPM_WIDTHB ; 10 ; Untyped ;; LPM_WIDTHP ; 20 ; Untyped ;; LPM_WIDTHR ; 20 ; Untyped ;; LPM_WIDTHS ; 1 ; Untyped ;; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;; LPM_PIPELINE ; 0 ; Untyped ;; LATENCY ; 0 ; Untyped ;; INPUT_A_IS_CONSTANT ; NO ; Untyped ;; INPUT_B_IS_CONSTANT ; NO ; Untyped ;; USE_EAB ; OFF ; Untyped ;; MAXIMIZE_SPEED ; 5 ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; CARRY_CHAIN ; MANUAL ; Untyped ;; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;; CBXI_PARAMETER ; mult_pu01 ; Untyped ;; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;+------------------------------------------------+------------+--------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------+; Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0 ;+------------------------+----------------+-----------------------------------------------+; Parameter Name ; Value ; Type ;+------------------------+----------------+-----------------------------------------------+; LPM_WIDTHN ; 20 ; Untyped ;; LPM_WIDTHD ; 7 ; Untyped ;; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;; LPM_PIPELINE ; 0 ; Untyped ;; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;; MAXIMIZE_SPEED ; 5 ; Untyped ;; CBXI_PARAMETER ; lpm_divide_aem ; Untyped ;; CARRY_CHAIN ; MANUAL ; Untyped ;; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;+------------------------+----------------+-----------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------+; Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0 ;+------------------------------------------------+------------+--------------------------+; Parameter Name ; Value ; Type ;+------------------------------------------------+------------+--------------------------+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; LPM_WIDTHA ; 10 ; Untyped ;; LPM_WIDTHB ; 10 ; Untyped ;; LPM_WIDTHP ; 20 ; Untyped ;; LPM_WIDTHR ; 20 ; Untyped ;; LPM_WIDTHS ; 1 ; Untyped ;; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;; LPM_PIPELINE ; 0 ; Untyped ;; LATENCY ; 0 ; Untyped ;; INPUT_A_IS_CONSTANT ; NO ; Untyped ;; INPUT_B_IS_CONSTANT ; NO ; Untyped ;; USE_EAB ; OFF ; Untyped ;; MAXIMIZE_SPEED ; 5 ; Untyped ;; DEVICE_FAMILY ; Cyclone II ; Untyped ;; CARRY_CHAIN ; MANUAL ; Untyped ;; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;; CBXI_PARAMETER ; mult_pu01 ; Untyped ;; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;+------------------------------------------------+------------+--------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------------+; Parameter Settings for Inferred Entity Instance: ADPCM_Decoder_1_Bit:u6|lpm_divide:Div0 ;+------------------------+----------------+-----------------------------------------------+; Parameter Name ; Value ; Type ;+------------------------+----------------+-----------------------------------------------+; LPM_WIDTHN ; 20 ; Untyped ;; LPM_WIDTHD ; 7 ; Untyped ;; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;; LPM_PIPELINE ; 0 ; Untyped ;; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;; MAXIMIZE_SPEED ; 5 ; Untyped ;; CBXI_PARAMETER ; lpm_divide_aem ; Untyped ;; CARRY_CHAIN ; MANUAL ; Untyped ;; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;+------------------------+----------------+-----------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-------------------------------------------------------------------------------+; lpm_mult Parameter Settings by Entity Instance ;+---------------------------------------+---------------------------------------+; Name ; Value ;+---------------------------------------+---------------------------------------+; Number of entity instances ; 2 ;; Entity Instance ; ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0 ;; -- LPM_WIDTHA ; 10 ;; -- LPM_WIDTHB ; 10 ;; -- LPM_WIDTHP ; 20 ;; -- LPM_REPRESENTATION ; UNSIGNED ;; -- INPUT_A_IS_CONSTANT ; NO ;; -- INPUT_B_IS_CONSTANT ; NO ;; -- USE_EAB ; OFF ;; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;; -- INPUT_A_FIXED_VALUE ; Bx ;; -- INPUT_B_FIXED_VALUE ; Bx ;; Entity Instance ; ADPCM_Decoder_1_Bit:u6|lpm_mult:Mult0 ;; -- LPM_WIDTHA ; 10 ;; -- LPM_WIDTHB ; 10 ;; -- LPM_WIDTHP ; 20 ;; -- LPM_REPRESENTATION ; UNSIGNED ;; -- INPUT_A_IS_CONSTANT ; NO ;; -- INPUT_B_IS_CONSTANT ; NO ;; -- USE_EAB ; OFF ;; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;; -- INPUT_A_FIXED_VALUE ; Bx ;; -- INPUT_B_FIXED_VALUE ; Bx ;+---------------------------------------+---------------------------------------++----------------------------------------------------------------------------------------------------------------------+; Port Connectivity Checks: "Flash_Memory_Driver:u4" ;+------------+--------+----------+-------------------------------------------------------------------------------------+; Port ; Type ; Severity ; Details ;+------------+--------+----------+-------------------------------------------------------------------------------------+; active_in ; Input ; Info ; Stuck at VCC ;; data_valid ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;+------------+--------+----------+-------------------------------------------------------------------------------------++-------------------------------------------------------+; Port Connectivity Checks: "I2C_Driver:u2" ;+---------------------+-------+----------+--------------+; Port ; Type ; Severity ; Details ;+---------------------+-------+----------+--------------+; slave_address[5..4] ; Input ; Info ; Stuck at VCC ;; slave_address[7..6] ; Input ; Info ; Stuck at GND ;; slave_address[1..0] ; Input ; Info ; Stuck at GND ;; slave_address[3] ; Input ; Info ; Stuck at GND ;; slave_address[2] ; Input ; Info ; Stuck at VCC ;+---------------------+-------+----------+--------------++-----------------------------------------------------+; Port Connectivity Checks: "SevenSegments_Driver:u0" ;+------------+-------+----------+---------------------+; Port ; Type ; Severity ; Details ;+------------+-------+----------+---------------------+; digit_1_in ; Input ; Info ; Stuck at GND ;; digit_2_in ; Input ; Info ; Stuck at GND ;; digit_3_in ; Input ; Info ; Stuck at GND ;; digit_4_in ; Input ; Info ; Stuck at GND ;+------------+-------+----------+---------------------++-------------------------------+; Analysis & Synthesis Messages ;+-------------------------------+Info: *******************************************************************Info: Running Quartus II Analysis & SynthesisInfo: Version 9.0 Build 132 02/25/2009 SJ Web EditionInfo: Processing started: Tue May 11 23:49:19 2010Info: Command: quartus_map --read_settings_files=on --write_settings_files=off HD_ADPCM_Codec -c HD_ADPCM_CodecInfo: Found 14 design units, including 7 entities, in source file HD_ADPCM_Codec.vhdInfo: Found design unit 1: HD_ADPCM_Codec-HD_ADPCM_Codec_FunctionInfo: Found design unit 2: SevenSegments_Driver-HD_ADPCM_Codec_FunctionInfo: Found design unit 3: LEDs_Bar_Driver-HD_ADPCM_Codec_FunctionInfo: Found design unit 4: I2C_Driver-HD_ADPCM_Codec_FunctionInfo: Found design unit 5: I2S_Driver-HD_ADPCM_Codec_FunctionInfo: Found design unit 6: Flash_Memory_Driver-HD_ADPCM_Codec_FunctionInfo: Found design unit 7: ADPCM_Decoder_1_Bit-HD_ADPCM_Codec_FunctionInfo: Found entity 1: HD_ADPCM_CodecInfo: Found entity 2: SevenSegments_DriverInfo: Found entity 3: LEDs_Bar_DriverInfo: Found entity 4: I2C_DriverInfo: Found entity 5: I2S_DriverInfo: Found entity 6: Flash_Memory_DriverInfo: Found entity 7: ADPCM_Decoder_1_BitInfo: Elaborating entity "HD_ADPCM_Codec" for the top level hierarchyWarning (10541): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(103): used implicit default value for signal "Seven_Segment_Digit1" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10541): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(104): used implicit default value for signal "Seven_Segment_Digit2" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10541): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(105): used implicit default value for signal "Seven_Segment_Digit3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10541): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(106): used implicit default value for signal "Seven_Segment_Digit4" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10540): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(127): used explicit default value for signal "I2C_SLAVE_ADDRESS" because signal was never assigned a valueWarning (10540): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(158): used explicit default value for signal "FLASH_MEMORY_ACTIVE" because signal was never assigned a valueWarning (10036): Verilog HDL or VHDL warning at HD_ADPCM_Codec.vhd(162): object "FLASH_MEMORY_DATA_VALID" assigned a value but never readInfo: Elaborating entity "SevenSegments_Driver" for hierarchy "SevenSegments_Driver:u0"Info: Elaborating entity "LEDs_Bar_Driver" for hierarchy "LEDs_Bar_Driver:u1"Info: Elaborating entity "I2C_Driver" for hierarchy "I2C_Driver:u2"Warning (10540): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(461): used explicit default value for signal "I2C_Data_Stream" because signal was never assigned a valueInfo: Elaborating entity "I2S_Driver" for hierarchy "I2S_Driver:u3"Warning (10540): VHDL Signal Declaration warning at HD_ADPCM_Codec.vhd(708): used explicit default value for signal "I2S_Data_Stream" because signal was never assigned a valueInfo: Elaborating entity "Flash_Memory_Driver" for hierarchy "Flash_Memory_Driver:u4"Info: Elaborating entity "ADPCM_Decoder_1_Bit" for hierarchy "ADPCM_Decoder_1_Bit:u5"Info: Found 1 instances of uninferred RAM logicInfo: RAM logic "I2C_Register_Address_Stream" is uninferred due to inappropriate RAM sizeInfo: Inferred 4 megafunctions from design logicInfo: Inferred multiplier megafunction ("lpm_mult") from the following logic: "ADPCM_Decoder_1_Bit:u5|Mult0"Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "ADPCM_Decoder_1_Bit:u5|Div0"Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "ADPCM_Decoder_1_Bit:u6|Mult0"Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "ADPCM_Decoder_1_Bit:u6|Div0"Info: Elaborated megafunction instantiation "ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0"Info: Instantiated megafunction "ADPCM_Decoder_1_Bit:u5|lpm_mult:Mult0" with the following parameter:Info: Parameter "LPM_WIDTHA" = "10"Info: Parameter "LPM_WIDTHB" = "10"Info: Parameter "LPM_WIDTHP" = "20"Info: Parameter "LPM_WIDTHR" = "20"Info: Parameter "LPM_WIDTHS" = "1"Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"Info: Parameter "MAXIMIZE_SPEED" = "5"Info: Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "AUTO"Info: Found 1 design units, including 1 entities, in source file db/mult_pu01.tdfInfo: Found entity 1: mult_pu01Info: Elaborated megafunction instantiation "ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0"Info: Instantiated megafunction "ADPCM_Decoder_1_Bit:u5|lpm_divide:Div0" with the following parameter:Info: Parameter "LPM_WIDTHN" = "20"Info: Parameter "LPM_WIDTHD" = "7"Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_aem.tdfInfo: Found entity 1: lpm_divide_aemInfo: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_klh.tdfInfo: Found entity 1: sign_div_unsign_klhInfo: Found 1 design units, including 1 entities, in source file db/alt_u_div_e2f.tdfInfo: Found entity 1: alt_u_div_e2fInfo: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdfInfo: Found entity 1: add_sub_lkcInfo: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdfInfo: Found entity 1: add_sub_mkcWarning: The following nodes have both tri-state and non-tri-state driversWarning: Inserted always-enabled tri-state buffer between "I2C_DATA_INOUT" and its non-tri-state driver.Warning: Inserted always-enabled tri-state buffer between "I2S_DATA_INOUT" and its non-tri-state driver.Warning: The following bidir pins have no driversWarning: Bidir "FLASH_MEMORY_DATA_INOUT[0]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[1]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[2]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[3]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[4]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[5]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[6]" has no driverWarning: Bidir "FLASH_MEMORY_DATA_INOUT[7]" has no driverWarning: TRI or OPNDRN buffers permanently enabledWarning: Node "I2C_DATA_INOUT~synth"Warning: Node "I2S_DATA_INOUT~synth"Warning: Output pins are stuck at VCC or GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[0]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[1]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[2]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[3]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[4]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[5]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_1_OUT[6]" is stuck at VCCWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[0]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[1]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[2]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[3]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[4]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[5]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_2_OUT[6]" is stuck at VCCWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[0]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[1]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[2]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[3]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[4]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[5]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_3_OUT[6]" is stuck at VCCWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[0]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[1]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[2]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[3]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[4]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[5]" is stuck at GNDWarning (13410): Pin "S_SEVEN_SEGMENT_4_OUT[6]" is stuck at VCCWarning (13410): Pin "FLASH_MEMORY_nWE_OUT" is stuck at VCCWarning (13410): Pin "FLASH_MEMORY_nRESET_OUT" is stuck at VCCInfo: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below.Info: Register "ADPCM_Decoder_1_Bit:u5|PCM_Data_Difference[16]" lost all its fanouts during netlist optimizations.Info: Register "ADPCM_Decoder_1_Bit:u5|Last_PCM_Data[16]" lost all its fanouts during netlist optimizations.Info: Register "ADPCM_Decoder_1_Bit:u6|PCM_Data_Difference[16]" lost all its fanouts during netlist optimizations.Info: Register "ADPCM_Decoder_1_Bit:u6|Last_PCM_Data[16]" lost all its fanouts during netlist optimizations.Warning: Design contains 1 input pin(s) that do not drive logicWarning (15610): No output dependent on input pin "SWITCH_0"Info: Implemented 1781 device resources after synthesis - the final resource count might be differentInfo: Implemented 4 input pinsInfo: Implemented 68 output pinsInfo: Implemented 10 bidirectional pinsInfo: Implemented 1695 logic cellsInfo: Implemented 4 DSP elementsInfo: Quartus II Analysis & Synthesis was successful. 0 errors, 57 warningsInfo: Peak virtual memory: 202 megabytesInfo: Processing ended: Tue May 11 23:49:36 2010Info: Elapsed time: 00:00:17Info: Total CPU time (on all processors): 00:00:16