OpenCores
URL https://opencores.org/ocsvn/axi_slave/axi_slave/trunk

Subversion Repositories axi_slave

[/] [axi_slave/] [trunk/] [src/] [base/] [def_axi_slave_static.txt] - Rev 13

Compare with Previous | Blame | View Log

<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
SWAP.GLOBAL MODEL_NAME AXI slave stub
  
VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus
VERIFY (ADDR_BITS <= 24) ##Memory size should not be too big to prevent maloc fail

GROUP STUB_AXI_A is {
    ID       ID_BITS                output
    ADDR     ADDR_BITS              output
    LEN      LEN_BITS               output
    SIZE     SIZE_BITS              output
    BURST    2                      output
    CACHE    4                      output
    PROT     3                      output
    LOCK     2                      output
    VALID    1                      output
    READY    1                      input
}

GROUP STUB_AXI_W is {
    ID        ID_BITS                output
    DATA      DATA_BITS              output
    STRB      DATA_BITS/8            output
    LAST      1                      output
    VALID     1                      output
    READY     1                      input
}

GROUP STUB_AXI_B is {
    ID        ID_BITS                input
    RESP      2                      input
    VALID     1                      input
    READY     1                      output
}

GROUP STUB_AXI_R is {
    ID        ID_BITS                input
    DATA      DATA_BITS              input
    RESP      2                      input
    LAST      1                      input
    VALID     1                      input
    READY     1                      output
}

GROUP STUB_AXI joins {
    GROUP STUB_AXI_A prefix_AW
    GROUP STUB_AXI_W prefix_W
    GROUP STUB_AXI_B prefix_B
    GROUP STUB_AXI_A prefix_AR
    GROUP STUB_AXI_R prefix_R
}

GROUP STUB_MEM is {
    WR        1            output
    RD        1            output
    ADDR_WR   ADDR_BITS    output
    ADDR_RD   ADDR_BITS    output
    DIN       DATA_BITS    output
    BSEL      DATA_BITS/8  output
    DOUT      DATA_BITS    input
}
  

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.