URL
https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk
Subversion Repositories cpu6502_true_cycle
[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [core.vhd] - Rev 24
Go to most recent revision | Compare with Previous | Blame | View Log
-- VHDL Entity R6502_TC.Core.symbol -- -- Created: -- by - eda.UNKNOWN (ENTW1) -- at - 14:13:52 08.03.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Core IS PORT( clk_clk_i : IN std_logic; d_i : IN std_logic_vector (7 DOWNTO 0); irq_n_i : IN std_logic; nmi_n_i : IN std_logic; rdy_i : IN std_logic; rst_rst_n_i : IN std_logic; so_n_i : IN std_logic; a_o : OUT std_logic_vector (15 DOWNTO 0); d_o : OUT std_logic_vector (7 DOWNTO 0); rd_o : OUT std_logic; sync_o : OUT std_logic; wr_n_o : OUT std_logic; wr_o : OUT std_logic ); -- Declarations END Core ; -- Jens-D. Gutschmidt Project: R6502_TC -- scantara2003@yahoo.de -- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version -- 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A -- PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- CVS Revisins History -- -- $Log: struct.bd,v $ -- <<-- more -->> -- Title: Core -- Path: R6502_TC/Core/struct -- Edited: by eda on 08 Feb 2010 -- -- VHDL Architecture R6502_TC.Core.struct -- -- Created: -- by - eda.UNKNOWN (ENTW1) -- at - 14:13:53 08.03.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY R6502_TC; ARCHITECTURE struct OF Core IS -- Architecture declarations -- Internal signal declarations SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_alu_n_o_i : std_logic; SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_alu_or_o_i : std_logic; SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL ld_pc_o_i : std_logic; SIGNAL ld_sp_o_i : std_logic; SIGNAL load_regs_o_i : std_logic; SIGNAL nmi_o_i : std_logic; SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL reg_0flag_o_i : std_logic; SIGNAL reg_1flag_o_i : std_logic; SIGNAL reg_7flag_o_i : std_logic; SIGNAL rst_nmi_o_i : std_logic; SIGNAL sel_pc_in_o_i : std_logic; SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_sp_as_o_i : std_logic; SIGNAL sel_sp_in_o_i : std_logic; -- Component Declarations COMPONENT FSM_Execution_Unit PORT ( adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_sp_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic ; d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 ); irq_n_i : IN std_logic ; nmi_i : IN std_logic ; q_a_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_x_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_y_i : IN std_logic_vector ( 7 DOWNTO 0 ); rdy_i : IN std_logic ; reg_0flag_i : IN std_logic ; reg_1flag_i : IN std_logic ; reg_7flag_i : IN std_logic ; rst_rst_n_i : IN std_logic ; so_n_i : IN std_logic ; a_o : OUT std_logic_vector (15 DOWNTO 0); adr_o : OUT std_logic_vector (15 DOWNTO 0); ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ld_o : OUT std_logic_vector ( 1 DOWNTO 0 ); ld_pc_o : OUT std_logic ; ld_sp_o : OUT std_logic ; load_regs_o : OUT std_logic ; offset_o : OUT std_logic_vector ( 15 DOWNTO 0 ); rd_o : OUT std_logic ; rst_nmi_o : OUT std_logic ; sel_pc_in_o : OUT std_logic ; sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_sp_as_o : OUT std_logic ; sel_sp_in_o : OUT std_logic ; sync_o : OUT std_logic ; wr_n_o : OUT std_logic ; wr_o : OUT std_logic ); END COMPONENT; COMPONENT FSM_NMI PORT ( clk_clk_i : IN std_logic ; nmi_n_i : IN std_logic ; rst_nmi_i : IN std_logic ; rst_rst_n_i : IN std_logic ; nmi_o : OUT std_logic ); END COMPONENT; COMPONENT RegBank_AXY PORT ( clk_clk_i : IN std_logic ; d_regs_in_i : IN std_logic_vector (7 DOWNTO 0); load_regs_i : IN std_logic ; rst_rst_n_i : IN std_logic ; sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0); sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0); sel_reg_i : IN std_logic_vector (1 DOWNTO 0); d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0); q_a_o : OUT std_logic_vector (7 DOWNTO 0); q_x_o : OUT std_logic_vector (7 DOWNTO 0); q_y_o : OUT std_logic_vector (7 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_PC PORT ( adr_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic ; ld_i : IN std_logic_vector (1 DOWNTO 0); ld_pc_i : IN std_logic ; offset_i : IN std_logic_vector (15 DOWNTO 0); rst_rst_n_i : IN std_logic ; sel_pc_in_i : IN std_logic ; sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0); adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0); adr_pc_o : OUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_SP PORT ( adr_low_i : IN std_logic_vector (7 DOWNTO 0); clk_clk_i : IN std_logic ; ld_low_i : IN std_logic ; ld_sp_i : IN std_logic ; rst_rst_n_i : IN std_logic ; sel_sp_as_i : IN std_logic ; sel_sp_in_i : IN std_logic ; adr_sp_o : OUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit; FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI; FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY; FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC; FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP; -- pragma synthesis_on BEGIN -- ModuleWare code(v1.9) for instance 'U_11' of 'add' u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i) VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0); VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0); VARIABLE temp_sum : unsigned(8 DOWNTO 0); VARIABLE temp_carry : std_logic; BEGIN temp_din0 := '0' & ch_a_o_i; temp_din1 := '0' & ch_b_o_i; temp_carry := '0'; temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8); reg_0flag_o_i <= temp_sum(8) ; END PROCESS u_11combo_proc; -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' reg_1flag_o_i <= NOT(d_alu_or_o_i); -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' reg_7flag_o_i <= NOT(d_alu_n_o_i); -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' d_alu_n_o_i <= NOT(d_alu_o_i(7)); -- ModuleWare code(v1.9) for instance 'U_7' of 'por' d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7); -- Instance port mappings. U_4 : FSM_Execution_Unit PORT MAP ( adr_nxt_pc_i => adr_nxt_pc_o_i, adr_pc_i => adr_pc_o_i, adr_sp_i => adr_sp_o_i, clk_clk_i => clk_clk_i, d_alu_i => d_alu_o_i, d_i => d_i, d_regs_out_i => d_regs_out_o_i, irq_n_i => irq_n_i, nmi_i => nmi_o_i, q_a_i => q_a_o_i, q_x_i => q_x_o_i, q_y_i => q_y_o_i, rdy_i => rdy_i, reg_0flag_i => reg_0flag_o_i, reg_1flag_i => reg_1flag_o_i, reg_7flag_i => reg_7flag_o_i, rst_rst_n_i => rst_rst_n_i, so_n_i => so_n_i, a_o => a_o, adr_o => adr_o_i, ch_a_o => ch_a_o_i, ch_b_o => ch_b_o_i, d_o => d_o, d_regs_in_o => d_regs_in_o_i, ld_o => ld_o_i, ld_pc_o => ld_pc_o_i, ld_sp_o => ld_sp_o_i, load_regs_o => load_regs_o_i, offset_o => offset_o_i, rd_o => rd_o, rst_nmi_o => rst_nmi_o_i, sel_pc_in_o => sel_pc_in_o_i, sel_pc_val_o => sel_pc_val_o_i, sel_rb_in_o => sel_rb_in_o_i, sel_rb_out_o => sel_rb_out_o_i, sel_reg_o => sel_reg_o_i, sel_sp_as_o => sel_sp_as_o_i, sel_sp_in_o => sel_sp_in_o_i, sync_o => sync_o, wr_n_o => wr_n_o, wr_o => wr_o ); U_6 : FSM_NMI PORT MAP ( clk_clk_i => clk_clk_i, nmi_n_i => nmi_n_i, rst_nmi_i => rst_nmi_o_i, rst_rst_n_i => rst_rst_n_i, nmi_o => nmi_o_i ); U_2 : RegBank_AXY PORT MAP ( clk_clk_i => clk_clk_i, d_regs_in_i => d_regs_in_o_i, load_regs_i => load_regs_o_i, rst_rst_n_i => rst_rst_n_i, sel_rb_in_i => sel_rb_in_o_i, sel_rb_out_i => sel_rb_out_o_i, sel_reg_i => sel_reg_o_i, d_regs_out_o => d_regs_out_o_i, q_a_o => q_a_o_i, q_x_o => q_x_o_i, q_y_o => q_y_o_i ); U_0 : Reg_PC PORT MAP ( adr_i => adr_o_i, clk_clk_i => clk_clk_i, ld_i => ld_o_i, ld_pc_i => ld_pc_o_i, offset_i => offset_o_i, rst_rst_n_i => rst_rst_n_i, sel_pc_in_i => sel_pc_in_o_i, sel_pc_val_i => sel_pc_val_o_i, adr_nxt_pc_o => adr_nxt_pc_o_i, adr_pc_o => adr_pc_o_i ); U_1 : Reg_SP PORT MAP ( adr_low_i => adr_o_i(7 DOWNTO 0), clk_clk_i => clk_clk_i, ld_low_i => ld_o_i(0), ld_sp_i => ld_sp_o_i, rst_rst_n_i => rst_rst_n_i, sel_sp_as_i => sel_sp_as_o_i, sel_sp_in_i => sel_sp_in_o_i, adr_sp_o => adr_sp_o_i ); END struct;
Go to most recent revision | Compare with Previous | Blame | View Log