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-- VHDL Entity r6502_tc.fsm_execution_unit.symbol -- -- Created: -- by - eda.UNKNOWN (ENTW-7HPZ200) -- at - 11:35:43 11.09.2018 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity fsm_execution_unit is port( adr_nxt_pc_i : in std_logic_vector (15 downto 0); adr_pc_i : in std_logic_vector (15 downto 0); adr_sp_i : in std_logic_vector (15 downto 0); clk_clk_i : in std_logic; d_alu_i : in std_logic_vector ( 7 downto 0 ); d_i : in std_logic_vector ( 7 downto 0 ); d_regs_out_i : in std_logic_vector ( 7 downto 0 ); irq_n_i : in std_logic; nmi_i : in std_logic; q_a_i : in std_logic_vector ( 7 downto 0 ); q_x_i : in std_logic_vector ( 7 downto 0 ); q_y_i : in std_logic_vector ( 7 downto 0 ); rdy_i : in std_logic; reg_0flag_i : in std_logic; reg_1flag_i : in std_logic; reg_7flag_i : in std_logic; rst_rst_n_i : in std_logic; so_n_i : in std_logic; a_o : out std_logic_vector (15 downto 0); adr_o : out std_logic_vector (15 downto 0); ch_a_o : out std_logic_vector ( 7 downto 0 ); ch_b_o : out std_logic_vector ( 7 downto 0 ); d_o : out std_logic_vector ( 7 downto 0 ); d_regs_in_o : out std_logic_vector ( 7 downto 0 ); int_fetch_o : out std_logic; int_reg_2flag_o : out std_logic; ld_o : out std_logic_vector ( 1 downto 0 ); ld_pc_o : out std_logic; ld_sp_o : out std_logic; load_regs_o : out std_logic; offset_o : out std_logic_vector ( 15 downto 0 ); rd_o : out std_logic; rst_nmi_o : out std_logic; sel_pc_in_o : out std_logic; sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); sel_reg_o : out std_logic_vector ( 1 downto 0 ); sel_sp_as_o : out std_logic; sel_sp_in_o : out std_logic; sync_o : out std_logic; wr_n_o : out std_logic; wr_o : out std_logic ); -- Declarations end fsm_execution_unit ; -- (C) 2008 - 2018 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.11 2018/09/11 11:50:00 jens -- - RESET generates SYNC now, 1 dead cycle delayed -- - ADC / SBC flags and A like R6502 now -- - Bug Fix ADC and SBC in decimal mode (all op codes - -- "Overflow" flag was computed wrong) -- - Interrupt priority order is now: BRK - NMI - IRQ -- - Performance improvements on-going (Mealy -> Moore) -- - Bug Fixes All Branch Instructions -- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS) -- 3 cycles now if branch forward occur and the branch -- instruction lies on a xxFEh location. -- - Bug Fix Hardware Interrupts NMI & IRQ - "SYNC" now -- -- Revision 1.11 BETA 2013/07/24 15:46:00 jens -- - Changing the title block and internal revision history -- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong) -- -- Revision 1.10 2010/02/08 17:34:20 eda -- BUGFIX for IRQn, NMIn and RTI -- After detection of NMI or IRQ the address of the next instruction stacked wrong. -- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the -- vector address is not loaded yet. -- -- Revision 1.9 2010/02/08 17:32:19 eda -- BUGFIX for IRQn, NMIn and RTI -- After detection of NMI or IRQ the address of the next instruction stacked wrong. -- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the -- vector address is not loaded yet. -- -- Revision 1.8 2009/01/04 20:23:42 eda -- *** EMERGENCY BUGFIX *** -- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. -- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist -- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from -- $02FF and $0200, instead of $02FF and $0300) -- -- Revision 1.7 2009/01/04 16:54:59 eda -- - Removed unused bits in ALU (zw_ALUx) -- -- Revision 1.6 2009/01/04 10:27:49 eda -- Changes for cosmetic issues only -- -- Revision 1.5 2009/01/04 10:25:04 eda -- Changes for cosmetic issues only -- -- Revision 1.4 2009/01/03 16:53:01 eda -- - Unused nets and blocks deleted -- - Re-arragend symbols in block FSM_Execution_Unit -- - Renamed blocks -- - Input SO implemented -- -- Revision 1.3 2009/01/03 16:42:02 eda -- - Unused nets and blocks deleted -- - Re-arragend symbols in block FSM_Execution_Unit -- - Renamed blocks -- - Input SO implemented -- -- Revision 1.2 2008/12/31 19:31:24 eda -- Production Release -- -- -- -- VHDL Architecture r6502_tc.fsm_execution_unit.fsm -- -- Created: -- by - eda.UNKNOWN (ENTW-7HPZ200) -- at - 22:31:13 15.09.2018 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) -- -- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; architecture fsm of fsm_execution_unit is -- Architecture Declarations signal reg_F : std_logic_vector( 7 DOWNTO 0 ); signal reg_sel_pc_in : std_logic; signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_sp_as : std_logic; signal reg_sel_sp_in : std_logic; signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); signal sig_PC : std_logic_vector(15 DOWNTO 0); signal sig_RD : std_logic; signal sig_RWn : std_logic; signal sig_SYNC : std_logic; signal sig_WR : std_logic; signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); signal zw_alu : std_logic_vector(9 DOWNTO 0); signal zw_alu1 : std_logic_vector(9 DOWNTO 0); signal zw_alu2 : std_logic_vector(9 DOWNTO 0); signal zw_alu3 : std_logic_vector(9 DOWNTO 0); signal zw_alu4 : std_logic_vector(9 DOWNTO 0); signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); signal zw_bit : std_logic; signal zw_irq : std_logic; signal zw_ninebits4 : std_logic_vector(8 DOWNTO 0); signal zw_nmi : std_logic; signal zw_so : std_logic; subtype state_type is std_logic_vector(7 downto 0); -- Hard encoding constant FETCH : state_type := "00000000"; constant s0001 : state_type := "00000001"; constant s0101 : state_type := "00000011"; constant s0201 : state_type := "00000010"; constant s0301 : state_type := "00000110"; constant s0401 : state_type := "00000111"; constant s1001 : state_type := "00000101"; constant s1101 : state_type := "00000100"; constant s1201 : state_type := "00001100"; constant s1301 : state_type := "00001101"; constant s1501 : state_type := "00001111"; constant s1601 : state_type := "00001110"; constant s1602 : state_type := "00001010"; constant s1603 : state_type := "00001011"; constant s1604 : state_type := "00001001"; constant s2601 : state_type := "00001000"; constant s2605 : state_type := "00011000"; constant s2604 : state_type := "00011001"; constant s2603 : state_type := "00011011"; constant s2602 : state_type := "00011010"; constant s2606 : state_type := "00011110"; constant s2607 : state_type := "00011111"; constant s2608 : state_type := "00011101"; constant s2609 : state_type := "00011100"; constant s2610 : state_type := "00010100"; constant s2611 : state_type := "00010101"; constant s1901 : state_type := "00010111"; constant s1902 : state_type := "00010110"; constant s2001 : state_type := "00010010"; constant s2002 : state_type := "00010011"; constant s2101 : state_type := "00010001"; constant s2102 : state_type := "00010000"; constant s2103 : state_type := "00110000"; constant s2201 : state_type := "00110001"; constant s2202 : state_type := "00110011"; constant s2203 : state_type := "00110010"; constant s2301 : state_type := "00110110"; constant s2302 : state_type := "00110111"; constant s2303 : state_type := "00110101"; constant s2304 : state_type := "00110100"; constant s2305 : state_type := "00111100"; constant s2401 : state_type := "00111101"; constant s2402 : state_type := "00111111"; constant s2403 : state_type := "00111110"; constant s2404 : state_type := "00111010"; constant s2405 : state_type := "00111011"; constant s1701 : state_type := "00111001"; constant s1702 : state_type := "00111000"; constant s1703 : state_type := "00101000"; constant s1704 : state_type := "00101001"; constant s1705 : state_type := "00101011"; constant s0901 : state_type := "00101010"; constant s0902 : state_type := "00101110"; constant s0903 : state_type := "00101111"; constant s9901 : state_type := "00101101"; constant s9903 : state_type := "00101100"; constant s9904 : state_type := "00100100"; constant s9905 : state_type := "00100101"; constant s9906 : state_type := "00100111"; constant s9902 : state_type := "00100110"; constant s2801 : state_type := "00100010"; constant s2901 : state_type := "00100011"; constant s3001 : state_type := "00100001"; constant s3101 : state_type := "00100000"; constant s1801 : state_type := "01100000"; constant s1803 : state_type := "01100001"; constant s1805 : state_type := "01100011"; constant s1806 : state_type := "01100010"; constant s1802 : state_type := "01100110"; constant s1804 : state_type := "01100111"; constant s1808 : state_type := "01100101"; constant s1807 : state_type := "01100100"; constant s1810 : state_type := "01101100"; constant s1809 : state_type := "01101101"; constant s1401 : state_type := "01101111"; constant s1403 : state_type := "01101110"; constant s1404 : state_type := "01101010"; constant s1402 : state_type := "01101011"; constant s1405 : state_type := "01101001"; constant s1406 : state_type := "01101000"; constant s1407 : state_type := "01111000"; constant s1408 : state_type := "01111001"; constant s0801 : state_type := "01111011"; constant s0803 : state_type := "01111010"; constant s0802 : state_type := "01111110"; constant s0601 : state_type := "01111111"; constant s0603 : state_type := "01111101"; constant s0604 : state_type := "01111100"; constant s0602 : state_type := "01110100"; constant s0605 : state_type := "01110101"; constant s0606 : state_type := "01110111"; constant s0607 : state_type := "01110110"; constant s0608 : state_type := "01110010"; constant s0501 : state_type := "01110011"; constant s0503 : state_type := "01110001"; constant s0505 : state_type := "01110000"; constant s0506 : state_type := "01010000"; constant s0502 : state_type := "01010001"; constant s0504 : state_type := "01010011"; constant s0507 : state_type := "01010010"; constant s0509 : state_type := "01010110"; constant s0510 : state_type := "01010111"; constant s0508 : state_type := "01010101"; constant s0701 : state_type := "01010100"; constant s0702 : state_type := "01011100"; constant s0703 : state_type := "01011101"; constant s2501 : state_type := "01011111"; constant s2503 : state_type := "01011110"; constant s2505 : state_type := "01011010"; constant s2506 : state_type := "01011011"; constant s2502 : state_type := "01011001"; constant s2504 : state_type := "01011000"; constant s2507 : state_type := "01001000"; constant s2508 : state_type := "01001001"; constant s2509 : state_type := "01001011"; constant s2510 : state_type := "01001010"; constant s2701 : state_type := "01001110"; constant s2702 : state_type := "01001111"; constant s2703 : state_type := "01001101"; constant s2704 : state_type := "01001100"; constant s2707 : state_type := "01000100"; constant s2706 : state_type := "01000101"; constant s2705 : state_type := "01000111"; constant s0905 : state_type := "01000110"; constant s0907 : state_type := "01000010"; constant s0906 : state_type := "01000011"; constant s0904 : state_type := "01000001"; constant RES : state_type := "01000000"; constant RES7 : state_type := "11000000"; -- Declare current and next state signals signal current_state : state_type; signal next_state : state_type; -- Declare any pre-registered internal signals signal d_o_cld : std_logic_vector ( 7 downto 0 ); signal rd_o_cld : std_logic ; signal sync_o_cld : std_logic ; signal wr_n_o_cld : std_logic ; signal wr_o_cld : std_logic ; begin ----------------------------------------------------------------- clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then current_state <= RES; -- Default Reset Values d_o_cld <= X"00"; rd_o_cld <= '0'; sync_o_cld <= '0'; wr_n_o_cld <= '1'; wr_o_cld <= '0'; reg_F <= "00110100"; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_rb_in <= "00"; reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_sp_as <= '0'; reg_sel_sp_in <= '0'; sig_PC <= X"0000"; zw_REG_OP <= X"00"; zw_b1 <= X"00"; zw_b2 <= X"00"; zw_b3 <= X"00"; zw_b4 <= X"00"; zw_bit <= '0'; zw_irq <= '0'; zw_nmi <= '0'; zw_so <= '0'; elsif (clk_clk_i'event and clk_clk_i = '1') then current_state <= next_state; -- Default Assignment To Internals reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); reg_sel_pc_in <= reg_sel_pc_in; reg_sel_pc_val <= reg_sel_pc_val; reg_sel_rb_in <= reg_sel_rb_in; reg_sel_rb_out <= reg_sel_rb_out; reg_sel_reg <= reg_sel_reg; reg_sel_sp_as <= reg_sel_sp_as; reg_sel_sp_in <= reg_sel_sp_in; sig_PC <= sig_PC; zw_REG_OP <= zw_REG_OP; zw_b1 <= zw_b1; zw_b2 <= zw_b2; zw_b3 <= zw_b3; zw_b4 <= zw_b4; zw_bit <= zw_bit; zw_irq <= zw_irq; zw_nmi <= zw_nmi; zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); d_o_cld <= sig_D_OUT; rd_o_cld <= sig_RD; sync_o_cld <= sig_SYNC; wr_n_o_cld <= sig_RWn; wr_o_cld <= sig_WR; -- Combined Actions case current_state is when FETCH => zw_REG_OP <= d_i; if ((d_i = X"00") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((nmi_i = '1') and (rdy_i = '1')) then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; zw_nmi <= '0'; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; zw_irq <= '0'; elsif ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"24" or d_i = X"2C") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"18") and (rdy_i = '1')) then elsif ((d_i = X"D8") and (rdy_i = '1')) then elsif ((d_i = X"58") and (rdy_i = '1')) then reg_F(2) <= '0'; elsif ((d_i = X"B8") and (rdy_i = '1')) then elsif ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") and (rdy_i = '1')) then zw_b4 <= X"FF"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"CA") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; elsif ((d_i = X"88") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; elsif ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") and (rdy_i = '1')) then zw_b4 <= X"01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"E8") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; elsif ((d_i = X"C8") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; elsif ((d_i = X"4C" or d_i = X"6C") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"20") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1") and (rdy_i = '1')) then reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") and (rdy_i = '1')) then reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") and (rdy_i = '1')) then reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"EA") and (rdy_i = '1')) then elsif ((d_i = X"48") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"08") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"68") and (rdy_i = '1')) then reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"28") and (rdy_i = '1')) then reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"40") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"60") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"38") and (rdy_i = '1')) then elsif ((d_i = X"F8") and (rdy_i = '1')) then elsif ((d_i = X"78") and (rdy_i = '1')) then reg_F(2) <= '1'; elsif ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"86" or d_i = X"96" or d_i = X"8E") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"84" or d_i = X"94" or d_i = X"8C") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"AA") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "01"; reg_sel_rb_in <= "00"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"0A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"4A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"2A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"6A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"A8") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "10"; reg_sel_rb_in <= "00"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"98") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; reg_sel_reg <= "00"; reg_sel_rb_in <= "01"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"BA") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"8A") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "00"; reg_sel_rb_in <= "10"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"9A") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "11"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; end if; when s0001 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0101 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0201 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(3) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0301 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0401 => if (rdy_i = '1' and zw_REG_OP = X"9A") then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"BA") then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1001 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1101 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(3) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1201 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1301 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(6) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1501 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1601 => if (rdy_i = '1' and zw_REG_OP = X"4C") then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"6C") then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "00"; zw_b1 <= d_i; end if; when s1602 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; zw_b2 <= d_i; end if; when s1603 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; zw_b1 <= d_i; end if; when s1604 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2601 => if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"84")) then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"94")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"8C")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"9D") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"99") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"91") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"81") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"96") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; end if; when s2605 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s2604 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s2603 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s2602 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s2606 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s2607 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s2608 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s2609 => if (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s2610 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s2611 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when s1901 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s1902 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when s2001 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2002 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when s2102 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2103 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2202 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2203 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7 downto 6) <= d_i(7 downto 6); reg_F(3 downto 0) <= d_i(3 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2301 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2302 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2303 => if (rdy_i = '1') then sig_PC <= adr_sp_i; reg_F <= d_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; end if; when s2304 => if (rdy_i = '1') then sig_PC <= adr_sp_i; zw_b1 <= d_i; end if; when s2305 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2401 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2402 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2403 => if (rdy_i = '1') then sig_PC <= adr_sp_i; zw_b1 <= d_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "00"; end if; when s2404 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s2405 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1701 => if (rdy_i = '1') then sig_PC <= adr_sp_i; zw_b1 <= d_i; end if; when s1703 => sig_PC <= adr_sp_i; when s1704 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; when s1705 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1 (7 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0901 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s0902 => sig_PC <= adr_sp_i; when s0903 => sig_PC <= adr_sp_i; when s9901 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s9903 => reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s9904 => if (rdy_i = '1') then sig_PC <= adr_pc_i; end if; when s9905 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; end if; when s9906 => reg_F(2) <= '1'; reg_F(5) <= '1'; if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s9902 => reg_sel_pc_in <= '1'; reg_sel_pc_val <= "00"; if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2801 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(7); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2901 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s3001 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(7); reg_F(0) <= q_a_i(7); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s3101 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1801 => if (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then sig_PC <= X"00" & d_i; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"B6") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; end if; when s1803 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s1805 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s1806 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s1802 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s1804 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s1808 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s1807 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s1810 => if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s1809 => if ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s1401 => if (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s1403 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s1404 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s1402 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s1405 => if (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s1406 => if (rdy_i = '1') then zw_b1 <= d_alu_i; end if; when s1408 => sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when s0801 => if (rdy_i = '1' and zw_REG_OP = X"24") then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and zw_REG_OP = X"2C") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; end if; when s0803 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= d_i(7); reg_F(6) <= d_i(6); reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0802 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s0601 => if (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46")) then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; end if; when s0603 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s0604 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s0602 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s0605 => if (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s0607 => if (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) then zw_b1 <= d_i(6 downto 0) & '0'; zw_b2(0) <= d_i(7); elsif (rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) then zw_b1 <= '0' & d_i(7 downto 1); zw_b2(0) <= d_i(0); elsif (rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) then zw_b1 <= d_i(6 downto 0) & reg_F(0); zw_b2(0) <= d_i(7); elsif (rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) then zw_b1 <= reg_F(0) & d_i(7 downto 1); zw_b2(0) <= d_i(0); end if; when s0608 => sig_PC <= adr_pc_i; reg_F(0) <= zw_b2(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when s0501 => if (rdy_i = '1' and zw_REG_OP = X"65") then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_alu(7); reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7))); reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)); reg_F(0) <= zw_alu(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"75") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"6D") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"7D") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"79") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"71") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"61") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') then sig_PC <= adr_nxt_pc_i; reg_F(0) <= zw_alu(9) OR (zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR (zw_alu(8) AND zw_alu(7)) OR (zw_alu(8) AND zw_alu(6)); reg_F(1) <= (NOT(zw_alu(4) OR zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR (zw_alu(4) AND zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)))); reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); reg_F(7) <= zw_alu2(5); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0503 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s0505 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s0506 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s0502 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s0504 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s0507 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s0509 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_alu(7); reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7))); reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)); reg_F(0) <= zw_alu(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(0) <= zw_alu(9) OR (zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR (zw_alu(8) AND zw_alu(7)) OR (zw_alu(8) AND zw_alu(6)); reg_F(1) <= (NOT(zw_alu(4) OR zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR (zw_alu(4) AND zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)))); reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); reg_F(7) <= zw_alu2(5); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s0510 => if (rdy_i = '1' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_alu(7); reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (NOT zw_alu(7) AND (q_a_i(7)) AND (d_i(7))); reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)); reg_F(0) <= zw_alu(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(0) <= zw_alu(9) OR (zw_alu1(4) AND zw_alu(8) AND zw_alu(5)) OR (zw_alu(8) AND zw_alu(7)) OR (zw_alu(8) AND zw_alu(6)); reg_F(1) <= (NOT(zw_alu(4) OR zw_alu(8) OR zw_alu(7) OR zw_alu(6) OR zw_alu(5) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)) OR (zw_alu(4) AND zw_alu(8) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5) AND NOT(zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)))); reg_F(6) <= (zw_alu2(5) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); reg_F(7) <= zw_alu2(5); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0508 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s0701 => zw_b3 <= adr_nxt_pc_i (15 downto 8); if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "10"; zw_b2 <= d_i; end if; when s0702 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); end if; when s0703 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2501 => if (rdy_i = '1' and zw_REG_OP = X"E5") then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_alu(7); reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR (NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7))); reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)); reg_F(0) <= zw_alu(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"F5") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"ED") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"FD") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"F9") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"F1") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"E1") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') then sig_PC <= adr_nxt_pc_i; reg_F(0) <= (zw_alu2(4)); reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0)); reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7))); reg_F(7) <= zw_alu2(6); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2503 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s2505 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s2506 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s2502 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s2504 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s2507 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s2508 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s2509 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_alu(7); reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR (NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7))); reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)); reg_F(0) <= zw_alu(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(0) <= (zw_alu2(4)); reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0)); reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7))); reg_F(7) <= zw_alu2(6); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s2510 => if (rdy_i = '1' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_alu(7); reg_F(6) <= (zw_alu(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR (NOT zw_alu(7) AND (q_a_i(7)) AND (NOT d_i(7))); reg_F(1) <= NOT ((zw_alu(7)) OR zw_alu(6) OR zw_alu(5) OR zw_alu(4) OR zw_alu(3) OR zw_alu(2) OR zw_alu(1) OR zw_alu(0)); reg_F(0) <= zw_alu(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(0) <= (zw_alu2(4)); reg_F(1) <= NOT(zw_alu2(3) OR zw_alu2(2) OR zw_alu2(1) OR zw_alu2(0) OR zw_alu1(3) OR zw_alu1(2) OR zw_alu1(1) OR zw_alu1(0)); reg_F(6) <= (zw_alu2(3) XOR q_a_i(7)) AND ((q_a_i(7) XOR d_i(7))); reg_F(7) <= zw_alu2(6); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2701 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s2702 => sig_PC <= adr_sp_i; when s2703 => sig_PC <= adr_sp_i; when s2704 => if (nmi_i = '1') then sig_PC <= X"FFFA"; else sig_PC <= X"FFFE"; end if; when s2707 => reg_F(2) <= '1'; if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s2706 => if (rdy_i = '1') then sig_PC <= X"FFFB"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; zw_b1 <= d_i; end if; when s2705 => if (rdy_i = '1') then sig_PC <= X"FFFF"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; zw_b1 <= d_i; end if; when s0905 => if (rdy_i = '1') then sig_PC <= X"FFFF"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; zw_b1 <= d_i; end if; when s0907 => reg_F(2) <= '1'; if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s0906 => if (rdy_i = '1') then sig_PC <= X"FFFB"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "01"; zw_b1 <= d_i; end if; when s0904 => if (nmi_i = '1') then sig_PC <= X"FFFA"; else sig_PC <= X"FFFE"; end if; when RES => reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; when RES7 => sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when others => null; end case; end if; end process clocked_proc; ----------------------------------------------------------------- nextstate_proc : process ( adr_nxt_pc_i, adr_pc_i, adr_sp_i, current_state, d_alu_i, d_i, d_regs_out_i, irq_n_i, nmi_i, q_a_i, q_x_i, q_y_i, rdy_i, reg_F, reg_sel_pc_in, reg_sel_pc_val, reg_sel_rb_in, reg_sel_rb_out, reg_sel_reg, reg_sel_sp_as, reg_sel_sp_in, sig_PC, zw_REG_OP, zw_alu, zw_alu1, zw_alu2, zw_alu3, zw_b1, zw_b2, zw_b3, zw_b4 ) ----------------------------------------------------------------- begin -- Default Assignment a_o <= sig_PC; adr_o <= X"0000"; ch_a_o <= X"00"; ch_b_o <= X"00"; d_regs_in_o <= X"00"; int_fetch_o <= '0'; int_reg_2flag_o <= reg_F(2); ld_o <= "00"; ld_pc_o <= '0'; ld_sp_o <= '0'; load_regs_o <= '0'; offset_o <= X"0000"; rst_nmi_o <= '0'; sel_pc_in_o <= reg_sel_pc_in; sel_pc_val_o <= reg_sel_pc_val; sel_rb_in_o <= reg_sel_rb_in; sel_rb_out_o <= reg_sel_rb_out; sel_reg_o <= reg_sel_reg; sel_sp_as_o <= reg_sel_sp_as; sel_sp_in_o <= reg_sel_sp_in; -- Default Assignment To Internals sig_D_OUT <= X"00"; sig_RD <= '1'; sig_RWn <= '1'; sig_SYNC <= '0'; sig_WR <= '0'; zw_alu <= "00" & X"00"; zw_alu1 <= "00" & X"00"; zw_alu2 <= "00" & X"00"; zw_alu3 <= "00" & X"00"; zw_alu4 <= "00" & X"00"; zw_ninebits4 <= '0' & X"00"; -- Combined Actions case current_state is when FETCH => sig_RWn <= '1'; sig_RD <= '1'; sig_SYNC <= NOT (rdy_i); int_fetch_o <= '1'; if ((d_i = X"00") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0901; elsif ((nmi_i = '1') and (rdy_i = '1')) then next_state <= s2701; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then next_state <= s2701; elsif ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0501; elsif ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0601; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0701; elsif ((d_i = X"24" or d_i = X"2C") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0801; elsif ((d_i = X"18") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1001; elsif ((d_i = X"D8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1101; elsif ((d_i = X"58") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1201; elsif ((d_i = X"B8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1301; elsif ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1801; elsif ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1801; elsif ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1401; elsif ((d_i = X"CA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1501; elsif ((d_i = X"88") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1501; elsif ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1801; elsif ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1401; elsif ((d_i = X"E8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1501; elsif ((d_i = X"C8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1501; elsif ((d_i = X"4C" or d_i = X"6C") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1601; elsif ((d_i = X"20") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1701; elsif ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1801; elsif ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1801; elsif ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1801; elsif ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0601; elsif ((d_i = X"EA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0001; elsif ((d_i = X"48") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1901; elsif ((d_i = X"08") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2001; elsif ((d_i = X"68") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2101; elsif ((d_i = X"28") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2201; elsif ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0601; elsif ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0601; elsif ((d_i = X"40") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2301; elsif ((d_i = X"60") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2401; elsif ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2501; elsif ((d_i = X"38") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0101; elsif ((d_i = X"F8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0201; elsif ((d_i = X"78") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0301; elsif ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2601; elsif ((d_i = X"86" or d_i = X"96" or d_i = X"8E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2601; elsif ((d_i = X"84" or d_i = X"94" or d_i = X"8C") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2601; elsif ((d_i = X"AA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0401; elsif ((d_i = X"0A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2801; elsif ((d_i = X"4A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2901; elsif ((d_i = X"2A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s3001; elsif ((d_i = X"6A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s3101; elsif ((d_i = X"A8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0401; elsif ((d_i = X"98") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0401; elsif ((d_i = X"BA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0401; elsif ((d_i = X"8A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0401; elsif ((d_i = X"9A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0401; elsif (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0001; else next_state <= FETCH; end if; when s0001 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0001; end if; when s0101 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0101; end if; when s0201 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0201; end if; when s0301 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0301; end if; when s0401 => if (rdy_i = '1' and zw_REG_OP = X"9A") then adr_o <= X"01" & d_regs_out_i; ld_o <= "11"; ld_sp_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and zw_REG_OP = X"BA") then d_regs_in_o <= adr_sp_i (7 downto 0); ch_a_o <= adr_sp_i (7 downto 0); ch_b_o <= X"00"; load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then ch_a_o <= d_regs_out_i; ch_b_o <= X"00"; load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0401; end if; when s1001 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1001; end if; when s1101 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1101; end if; when s1201 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1201; end if; when s1301 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1301; end if; when s1501 => if (rdy_i = '1') then d_regs_in_o <= d_alu_i; ch_a_o <= d_regs_out_i; ch_b_o <= zw_b4; load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1501; end if; when s1601 => if (rdy_i = '1' and zw_REG_OP = X"4C") then ld_pc_o <= '1'; next_state <= s1604; elsif (rdy_i = '1' and zw_REG_OP = X"6C") then next_state <= s1602; else next_state <= s1601; end if; when s1602 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1603; else next_state <= s1602; end if; when s1603 => if (rdy_i = '1') then next_state <= s1604; else next_state <= s1603; end if; when s1604 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1604; end if; when s2601 => if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"84")) then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2611; elsif (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"94")) then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s2602; elsif (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"8C")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2603; elsif (rdy_i = '1' and zw_REG_OP = X"9D") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s2604; elsif (rdy_i = '1' and zw_REG_OP = X"99") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s2604; elsif (rdy_i = '1' and zw_REG_OP = X"91") then ch_a_o <= d_i; ch_b_o <= X"01"; next_state <= s2605; elsif (rdy_i = '1' and zw_REG_OP = X"81") then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s2606; elsif (rdy_i = '1' and zw_REG_OP = X"96") then ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s2602; else next_state <= s2601; end if; when s2605 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s2608; else next_state <= s2605; end if; when s2604 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2609; else next_state <= s2604; end if; when s2603 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2611; else next_state <= s2603; end if; when s2602 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2611; else next_state <= s2602; end if; when s2606 => if (rdy_i = '1') then next_state <= s2607; else next_state <= s2606; end if; when s2607 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; next_state <= s2610; else next_state <= s2607; end if; when s2608 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2609; else next_state <= s2608; end if; when s2609 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; next_state <= s2611; else next_state <= s2609; end if; when s2610 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2611; else next_state <= s2610; end if; when s2611 => sig_SYNC <= '1'; next_state <= FETCH; when s1901 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= q_a_i; ld_o <= "11"; ld_sp_o <= '1'; next_state <= s1902; else next_state <= s1901; end if; when s1902 => sig_SYNC <= '1'; next_state <= FETCH; when s2001 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F OR X"30"; ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2002; else next_state <= s2001; end if; when s2002 => sig_SYNC <= '1'; next_state <= FETCH; when s2101 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2102; else next_state <= s2101; end if; when s2102 => if (rdy_i = '1') then next_state <= s2103; else next_state <= s2102; end if; when s2103 => if (rdy_i = '1') then d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2103; end if; when s2201 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2202; else next_state <= s2201; end if; when s2202 => if (rdy_i = '1') then next_state <= s2203; else next_state <= s2202; end if; when s2203 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2203; end if; when s2301 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2302; else next_state <= s2301; end if; when s2302 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2303; else next_state <= s2302; end if; when s2303 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2304; else next_state <= s2303; end if; when s2304 => if (rdy_i = '1') then next_state <= s2305; else next_state <= s2304; end if; when s2305 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2305; end if; when s2401 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2402; else next_state <= s2401; end if; when s2402 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; next_state <= s2403; else next_state <= s2402; end if; when s2403 => if (rdy_i = '1') then next_state <= s2404; else next_state <= s2403; end if; when s2404 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2405; else next_state <= s2404; end if; when s2405 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2405; end if; when s1701 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; ld_pc_o <= '1'; next_state <= s1702; else next_state <= s1701; end if; when s1702 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); next_state <= s1703; else next_state <= s1702; end if; when s1703 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); next_state <= s1704; when s1704 => next_state <= s1705; when s1705 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1705; end if; when s0901 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; ld_pc_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_nxt_pc_i (15 downto 8); next_state <= s0902; else next_state <= s0901; end if; when s0902 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); next_state <= s0903; when s0903 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F OR ("001" & '1' & X"0"); next_state <= s0904; when s9901 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; next_state <= s9902; else next_state <= s9901; end if; when s9903 => adr_o <= X"FFFB"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; next_state <= s9904; else next_state <= s9903; end if; when s9904 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; next_state <= s9905; else next_state <= s9904; end if; when s9905 => if (rdy_i = '1') then next_state <= s9906; else next_state <= s9905; end if; when s9906 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s9906; end if; when s9902 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; next_state <= s9903; else next_state <= s9902; end if; when s2801 => if (rdy_i = '1') then ch_a_o <= q_a_i (6 downto 0) & '0'; ch_b_o <= X"00"; d_regs_in_o <= q_a_i (6 downto 0) & '0'; load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2801; end if; when s2901 => if (rdy_i = '1') then ch_a_o <= '0' & q_a_i (7 downto 1); ch_b_o <= X"00"; d_regs_in_o <= '0' & q_a_i (7 downto 1); load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2901; end if; when s3001 => if (rdy_i = '1') then ch_a_o <= q_a_i (6 downto 0) & reg_F(0); ch_b_o <= X"00"; d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0); load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s3001; end if; when s3101 => if (rdy_i = '1') then ch_a_o <= reg_F(0) & q_a_i (7 downto 1); ch_b_o <= X"00"; d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1); load_regs_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s3101; end if; when s1801 => if (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1810; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then ld_o <= "11"; ld_pc_o <= '1'; zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s1802; elsif (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1803; elsif (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s1805; elsif (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s1805; elsif (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) then ch_a_o <= d_i; ch_b_o <= X"01"; next_state <= s1806; elsif (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s1804; elsif (rdy_i = '1' and zw_REG_OP = X"B6") then ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s1802; else next_state <= s1801; end if; when s1803 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1810; else next_state <= s1803; end if; when s1805 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1809; else next_state <= s1805; end if; when s1806 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s1807; else next_state <= s1806; end if; when s1802 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1810; else next_state <= s1802; end if; when s1804 => if (rdy_i = '1') then next_state <= s1808; else next_state <= s1804; end if; when s1808 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; next_state <= s1803; else next_state <= s1808; end if; when s1807 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1809; else next_state <= s1807; end if; when s1810 => if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) then d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) then d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) then d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s1810; end if; when s1809 => if ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) then d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) then d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) then d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then zw_ALU <= unsigned ("00" & d_regs_out_i) + unsigned ("00" & NOT (d_i)) + 1; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' AND zw_b2(0) = '0') then d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s1810; else next_state <= s1809; end if; when s1401 => if (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1406; elsif (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s1402; elsif (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1403; elsif (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s1404; else next_state <= s1401; end if; when s1403 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1406; else next_state <= s1403; end if; when s1404 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1405; else next_state <= s1404; end if; when s1402 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s1406; else next_state <= s1402; end if; when s1405 => if (rdy_i = '1') then next_state <= s1406; else next_state <= s1405; end if; when s1406 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= zw_b4; next_state <= s1407; else next_state <= s1406; end if; when s1407 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b1; next_state <= s1408; else next_state <= s1407; end if; when s1408 => ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; when s0801 => if (rdy_i = '1' and zw_REG_OP = X"24") then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0803; elsif (rdy_i = '1' and zw_REG_OP = X"2C") then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0802; else next_state <= s0801; end if; when s0803 => if (rdy_i = '1') then ch_a_o <= q_a_i AND d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0803; end if; when s0802 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0803; else next_state <= s0802; end if; when s0601 => if (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s0604; elsif (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0606; elsif (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s0602; elsif (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E")) then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0603; else next_state <= s0601; end if; when s0603 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0606; else next_state <= s0603; end if; when s0604 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0605; else next_state <= s0604; end if; when s0602 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0606; else next_state <= s0602; end if; when s0605 => if (rdy_i = '1') then next_state <= s0606; else next_state <= s0605; end if; when s0606 => if (rdy_i = '1') then next_state <= s0607; else next_state <= s0606; end if; when s0607 => if (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) then sig_D_OUT <= d_i(6 downto 0) & '0'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; next_state <= s0608; elsif (rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) then sig_D_OUT <= '0' & d_i(7 downto 1); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; next_state <= s0608; elsif (rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) then sig_D_OUT <= d_i(6 downto 0) & reg_F(0); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; next_state <= s0608; elsif (rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) then sig_D_OUT <= reg_F(0) & d_i(7 downto 1); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; next_state <= s0608; else next_state <= s0607; end if; when s0608 => ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; next_state <= FETCH; when s0501 => if (rdy_i = '1' and zw_REG_OP = X"65") then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0510; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and zw_REG_OP = X"75") then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s0502; elsif (rdy_i = '1' and zw_REG_OP = X"6D") then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0503; elsif (rdy_i = '1' and zw_REG_OP = X"7D") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s0505; elsif (rdy_i = '1' and zw_REG_OP = X"79") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s0505; elsif (rdy_i = '1' and zw_REG_OP = X"71") then ch_a_o <= d_i; ch_b_o <= X"01"; next_state <= s0506; elsif (rdy_i = '1' and zw_REG_OP = X"61") then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s0504; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_alu3(7 downto 0); load_regs_o <= '1'; zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) + unsigned (zw_alu(8 downto 5)); zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) + unsigned (zw_alu(3 downto 0)); zw_alu2(3 downto 0) <= '0' & (zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) & (zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) & zw_alu1(4); zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR (NOT(zw_alu1(4)) AND zw_alu(8)) OR (zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5)); zw_alu2(6) <= zw_alu(9) OR (zw_alu(8) AND zw_alu(7)) OR (zw_alu(8) AND zw_alu(6)); zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5)); zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0'; zw_alu1(4) <= zw_alu(4) OR (zw_alu(3) AND zw_alu(2)) OR (zw_alu(3) AND zw_alu(1)); zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)); zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0501; end if; when s0503 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0510; else next_state <= s0503; end if; when s0505 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0509; else next_state <= s0505; end if; when s0506 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s0508; else next_state <= s0506; end if; when s0502 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0510; else next_state <= s0502; end if; when s0504 => if (rdy_i = '1') then next_state <= s0507; else next_state <= s0504; end if; when s0507 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; next_state <= s0503; else next_state <= s0507; end if; when s0509 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then d_regs_in_o <= zw_alu3(7 downto 0); load_regs_o <= '1'; zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) + unsigned (zw_alu(8 downto 5)); zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) + unsigned (zw_alu(3 downto 0)); zw_alu2(3 downto 0) <= '0' & (zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) & (zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) & zw_alu1(4); zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR (NOT(zw_alu1(4)) AND zw_alu(8)) OR (zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5)); zw_alu2(6) <= zw_alu(9) OR (zw_alu(8) AND zw_alu(7)) OR (zw_alu(8) AND zw_alu(6)); zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5)); zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0'; zw_alu1(4) <= zw_alu(4) OR (zw_alu(3) AND zw_alu(2)) OR (zw_alu(3) AND zw_alu(1)); zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)); zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s0510; else next_state <= s0509; end if; when s0510 => if (rdy_i = '1' and reg_F(3) = '0') then d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and reg_F(3) = '1') then d_regs_in_o <= zw_alu3(7 downto 0); load_regs_o <= '1'; zw_alu3(7 downto 4) <= unsigned (zw_alu2(3 downto 0)) + unsigned (zw_alu(8 downto 5)); zw_alu3(3 downto 0) <= unsigned (zw_alu1(3 downto 0)) + unsigned (zw_alu(3 downto 0)); zw_alu2(3 downto 0) <= '0' & (zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) & (zw_alu2(6) OR (zw_alu2(4) AND zw_alu1(4))) & zw_alu1(4); zw_alu2(5) <= (zw_alu1(4) AND zw_alu(8) AND (NOT(zw_alu(5)) OR NOT(zw_alu(6)) OR NOT(zw_alu(7)))) OR (NOT(zw_alu1(4)) AND zw_alu(8)) OR (zw_alu1(4) AND NOT(zw_alu(8)) AND zw_alu(7) AND zw_alu(6) AND zw_alu(5)); zw_alu2(6) <= zw_alu(9) OR (zw_alu(8) AND zw_alu(7)) OR (zw_alu(8) AND zw_alu(6)); zw_alu2(4) <= (zw_alu(8) AND NOT(zw_alu(7)) AND NOT(zw_alu(6)) AND zw_alu(5)); zw_alu1(3 downto 0) <= '0' & ((zw_alu1(4))) & ((zw_alu1(4))) & '0'; zw_alu1(4) <= zw_alu(4) OR (zw_alu(3) AND zw_alu(2)) OR (zw_alu(3) AND zw_alu(1)); zw_alu(9 downto 5) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)); zw_alu(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0510; end if; when s0508 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0509; else next_state <= s0508; end if; when s0701 => if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0702; else next_state <= s0701; end if; when s0702 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_o <= "11"; ld_pc_o <= '1'; next_state <= s0703; else next_state <= s0702; end if; when s0703 => if (rdy_i = '1') then sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0703; end if; when s2501 => if (rdy_i = '1' and zw_REG_OP = X"E5") then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2510; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and zw_REG_OP = X"F5") then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s2502; elsif (rdy_i = '1' and zw_REG_OP = X"ED") then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2503; elsif (rdy_i = '1' and zw_REG_OP = X"FD") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s2505; elsif (rdy_i = '1' and zw_REG_OP = X"F9") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s2505; elsif (rdy_i = '1' and zw_REG_OP = X"F1") then ch_a_o <= d_i; ch_b_o <= X"01"; next_state <= s2506; elsif (rdy_i = '1' and zw_REG_OP = X"E1") then ch_a_o <= d_i; ch_b_o <= q_x_i; next_state <= s2504; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) - unsigned (zw_alu3(7 downto 4)); zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) - unsigned (zw_alu3(3 downto 0)); zw_ALU3(7 downto 0) <= '0' & (NOT zw_alu2(4)) & (NOT zw_alu2(4)) & '0' & '0' & (NOT zw_alu1(4)) & (NOT zw_alu1(4)) & '0'; zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR (NOT(zw_alu1(4)) AND zw_alu2(3)) OR (zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0)); zw_alu2(6) <= (zw_alu2(3)); zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) + zw_alu1(4); zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2501; end if; when s2503 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2510; else next_state <= s2503; end if; when s2505 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2509; else next_state <= s2505; end if; when s2506 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; next_state <= s2507; else next_state <= s2506; end if; when s2502 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2510; else next_state <= s2502; end if; when s2504 => if (rdy_i = '1') then next_state <= s2508; else next_state <= s2504; end if; when s2507 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; next_state <= s2509; else next_state <= s2507; end if; when s2508 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; next_state <= s2503; else next_state <= s2508; end if; when s2509 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) - unsigned (zw_alu3(7 downto 4)); zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) - unsigned (zw_alu3(3 downto 0)); zw_ALU3(7 downto 0) <= '0' & (NOT zw_alu2(4)) & (NOT zw_alu2(4)) & '0' & '0' & (NOT zw_alu1(4)) & (NOT zw_alu1(4)) & '0'; zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR (NOT(zw_alu1(4)) AND zw_alu2(3)) OR (zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0)); zw_alu2(6) <= (zw_alu2(3)); zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) + zw_alu1(4); zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s2510; else next_state <= s2509; end if; when s2510 => if (rdy_i = '1' and reg_F(3) = '0') then d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_alu(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; elsif (rdy_i = '1' and reg_F(3) = '1') then d_regs_in_o <= zw_alu(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned ((zw_alu2(3 downto 0))) - unsigned (zw_alu3(7 downto 4)); zw_ALU(3 downto 0) <= unsigned ((zw_alu1(3 downto 0))) - unsigned (zw_alu3(3 downto 0)); zw_ALU3(7 downto 0) <= '0' & (NOT zw_alu2(4)) & (NOT zw_alu2(4)) & '0' & '0' & (NOT zw_alu1(4)) & (NOT zw_alu1(4)) & '0'; zw_alu2(5) <= (zw_alu1(4) AND zw_alu2(3) AND (NOT(zw_alu2(0)) OR NOT(zw_alu2(1)) OR NOT(zw_alu2(2)))) OR (NOT(zw_alu1(4)) AND zw_alu2(3)) OR (zw_alu1(4) AND NOT(zw_alu2(3)) AND zw_alu2(2) AND zw_alu2(1) AND zw_alu2(0)); zw_alu2(6) <= (zw_alu2(3)); zw_alu2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT(d_i(7 downto 4))) + zw_alu1(4); zw_alu1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT(d_i(3 downto 0))) + reg_F(0); sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2510; end if; when s2701 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); next_state <= s2702; else next_state <= s2701; end if; when s2702 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); next_state <= s2703; when s2703 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= (reg_F AND X"EF"); next_state <= s2704; when s2704 => if (nmi_i = '1') then next_state <= s2706; else next_state <= s2705; end if; when s2707 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; rst_nmi_o <= '1'; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s2707; end if; when s2706 => if (rdy_i = '1') then next_state <= s2707; else next_state <= s2706; end if; when s2705 => if (rdy_i = '1') then next_state <= s2707; else next_state <= s2705; end if; when s0905 => if (rdy_i = '1') then next_state <= s0907; else next_state <= s0905; end if; when s0907 => if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; next_state <= FETCH; else next_state <= s0907; end if; when s0906 => if (rdy_i = '1') then next_state <= s0907; else next_state <= s0906; end if; when s0904 => if (nmi_i = '1') then rst_nmi_o <= '1'; next_state <= s0906; else next_state <= s0905; end if; when RES => sig_RWn <= '1'; sig_RD <= '1'; sig_SYNC <= '1'; next_state <= RES7; when RES7 => ld_o <= "11"; ld_pc_o <= '1'; ld_sp_o <= '1'; sig_RWn <= '1'; sig_RD <= '1'; next_state <= s9901; when others => next_state <= RES; end case; end process nextstate_proc; -- Concurrent Statements -- Clocked output assignments d_o <= d_o_cld; rd_o <= rd_o_cld; sync_o <= sync_o_cld; wr_n_o <= wr_n_o_cld; wr_o <= wr_o_cld; end fsm;