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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [fsm_execution_unit.vhd] - Rev 6
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-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol -- -- Created: -- by - eda.UNKNOWN (TEST) -- at - 21:30:21 04.01.2009 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY FSM_Execution_Unit IS PORT( adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_sp_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic; d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 ); irq_n_i : IN std_logic; nmi_i : IN std_logic; q_a_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_x_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_y_i : IN std_logic_vector ( 7 DOWNTO 0 ); rdy_i : IN std_logic; reg_0flag_i : IN std_logic; reg_1flag_i : IN std_logic; reg_7flag_i : IN std_logic; rst_rst_n_i : IN std_logic; so_n_i : IN std_logic; a_o : OUT std_logic_vector (15 DOWNTO 0); adr_o : OUT std_logic_vector (15 DOWNTO 0); ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 ); fetch_o : OUT std_logic; ld_o : OUT std_logic_vector ( 1 DOWNTO 0 ); ld_pc_o : OUT std_logic; ld_sp_o : OUT std_logic; load_regs_o : OUT std_logic; offset_o : OUT std_logic_vector ( 15 DOWNTO 0 ); rd_o : OUT std_logic; sel_pc_as_o : OUT std_logic; sel_pc_in_o : OUT std_logic; sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_sp_as_o : OUT std_logic; sel_sp_in_o : OUT std_logic; sync_o : OUT std_logic; wr_n_o : OUT std_logic; wr_o : OUT std_logic ); -- Declarations END FSM_Execution_Unit ; -- Jens-D. Gutschmidt Project: R6502_TC -- scantara2003@yahoo.de -- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- CVS Revisins History -- -- $Log: not supported by cvs2svn $ -- <<-- more -->> -- Title: FSM Execution Unit for all op codes -- Path: R6502_TC/FSM_Execution_Unit/fsm -- Edited: by eda on 04 Jan 2009 -- -- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm -- -- Created: -- by - eda.UNKNOWN (TEST) -- at - 21:30:22 04.01.2009 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ARCHITECTURE fsm OF FSM_Execution_Unit IS -- Architecture Declarations SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 ); SIGNAL reg_PC : std_logic_vector(15 DOWNTO 0); SIGNAL reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); SIGNAL reg_sel_pc_as : std_logic; SIGNAL reg_sel_pc_in : std_logic; SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); SIGNAL reg_sel_sp_as : std_logic; SIGNAL reg_sel_sp_in : std_logic; SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0); SIGNAL sig_RD : std_logic; SIGNAL sig_RWn : std_logic; SIGNAL sig_SYNC : std_logic; SIGNAL sig_WR : std_logic; SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_ALU1 : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_ALU2 : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_ALU3 : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_ALU4 : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_ALU5 : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_ALU6 : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_PC : std_logic_vector( 15 DOWNTO 0 ); SIGNAL zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); SIGNAL zw_REG_NMI : std_logic; SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); SIGNAL zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 ); SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 ); SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 ); SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 ); SIGNAL zw_so : std_logic; SIGNAL zw_w1 : std_logic_vector( 15 DOWNTO 0 ); SIGNAL zw_w2 : std_logic_vector( 15 DOWNTO 0 ); SIGNAL zw_w3 : std_logic_vector( 15 DOWNTO 0 ); SUBTYPE STATE_TYPE IS std_logic_vector(7 DOWNTO 0); -- State vector declaration ATTRIBUTE state_vector : string; ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state"; -- Hard encoding CONSTANT FETCH : STATE_TYPE := "00000000"; CONSTANT s1 : STATE_TYPE := "00000001"; CONSTANT s2 : STATE_TYPE := "00000011"; CONSTANT s5 : STATE_TYPE := "00000010"; CONSTANT s3 : STATE_TYPE := "00000110"; CONSTANT s4 : STATE_TYPE := "00000111"; CONSTANT s12 : STATE_TYPE := "00000101"; CONSTANT s16 : STATE_TYPE := "00000100"; CONSTANT s17 : STATE_TYPE := "00001100"; CONSTANT s24 : STATE_TYPE := "00001101"; CONSTANT s25 : STATE_TYPE := "00001111"; CONSTANT s271 : STATE_TYPE := "00001110"; CONSTANT s273 : STATE_TYPE := "00001010"; CONSTANT s304 : STATE_TYPE := "00001011"; CONSTANT s307 : STATE_TYPE := "00001001"; CONSTANT s177 : STATE_TYPE := "00001000"; CONSTANT s180 : STATE_TYPE := "00011000"; CONSTANT s181 : STATE_TYPE := "00011001"; CONSTANT s182 : STATE_TYPE := "00011011"; CONSTANT s183 : STATE_TYPE := "00011010"; CONSTANT s184 : STATE_TYPE := "00011110"; CONSTANT s185 : STATE_TYPE := "00011111"; CONSTANT s186 : STATE_TYPE := "00011101"; CONSTANT s187 : STATE_TYPE := "00011100"; CONSTANT s188 : STATE_TYPE := "00010100"; CONSTANT s189 : STATE_TYPE := "00010101"; CONSTANT s190 : STATE_TYPE := "00010111"; CONSTANT s191 : STATE_TYPE := "00010110"; CONSTANT s192 : STATE_TYPE := "00010010"; CONSTANT s193 : STATE_TYPE := "00010011"; CONSTANT s377 : STATE_TYPE := "00010001"; CONSTANT s381 : STATE_TYPE := "00010000"; CONSTANT s378 : STATE_TYPE := "00110000"; CONSTANT s382 : STATE_TYPE := "00110001"; CONSTANT s379 : STATE_TYPE := "00110011"; CONSTANT s383 : STATE_TYPE := "00110010"; CONSTANT s384 : STATE_TYPE := "00110110"; CONSTANT s380 : STATE_TYPE := "00110111"; CONSTANT s385 : STATE_TYPE := "00110101"; CONSTANT s386 : STATE_TYPE := "00110100"; CONSTANT s387 : STATE_TYPE := "00111100"; CONSTANT s388 : STATE_TYPE := "00111101"; CONSTANT s389 : STATE_TYPE := "00111111"; CONSTANT s391 : STATE_TYPE := "00111110"; CONSTANT s392 : STATE_TYPE := "00111010"; CONSTANT s390 : STATE_TYPE := "00111011"; CONSTANT s393 : STATE_TYPE := "00111001"; CONSTANT s394 : STATE_TYPE := "00111000"; CONSTANT s395 : STATE_TYPE := "00101000"; CONSTANT s396 : STATE_TYPE := "00101001"; CONSTANT s397 : STATE_TYPE := "00101011"; CONSTANT s398 : STATE_TYPE := "00101010"; CONSTANT s399 : STATE_TYPE := "00101110"; CONSTANT s400 : STATE_TYPE := "00101111"; CONSTANT s401 : STATE_TYPE := "00101101"; CONSTANT s526 : STATE_TYPE := "00101100"; CONSTANT s527 : STATE_TYPE := "00100100"; CONSTANT s528 : STATE_TYPE := "00100101"; CONSTANT s529 : STATE_TYPE := "00100111"; CONSTANT s530 : STATE_TYPE := "00100110"; CONSTANT s531 : STATE_TYPE := "00100010"; CONSTANT s544 : STATE_TYPE := "00100011"; CONSTANT s545 : STATE_TYPE := "00100001"; CONSTANT s546 : STATE_TYPE := "00100000"; CONSTANT s547 : STATE_TYPE := "01100000"; CONSTANT s549 : STATE_TYPE := "01100001"; CONSTANT s550 : STATE_TYPE := "01100011"; CONSTANT s404 : STATE_TYPE := "01100010"; CONSTANT s556 : STATE_TYPE := "01100110"; CONSTANT s557 : STATE_TYPE := "01100111"; CONSTANT s579 : STATE_TYPE := "01100101"; CONSTANT s201 : STATE_TYPE := "01100100"; CONSTANT s202 : STATE_TYPE := "01101100"; CONSTANT s210 : STATE_TYPE := "01101101"; CONSTANT s211 : STATE_TYPE := "01101111"; CONSTANT s215 : STATE_TYPE := "01101110"; CONSTANT s217 : STATE_TYPE := "01101010"; CONSTANT s218 : STATE_TYPE := "01101011"; CONSTANT s222 : STATE_TYPE := "01101001"; CONSTANT s223 : STATE_TYPE := "01101000"; CONSTANT s224 : STATE_TYPE := "01111000"; CONSTANT s225 : STATE_TYPE := "01111001"; CONSTANT s226 : STATE_TYPE := "01111011"; CONSTANT s243 : STATE_TYPE := "01111010"; CONSTANT s244 : STATE_TYPE := "01111110"; CONSTANT s247 : STATE_TYPE := "01111111"; CONSTANT s344 : STATE_TYPE := "01111101"; CONSTANT s343 : STATE_TYPE := "01111100"; CONSTANT s250 : STATE_TYPE := "01110100"; CONSTANT s251 : STATE_TYPE := "01110101"; CONSTANT s351 : STATE_TYPE := "01110111"; CONSTANT s361 : STATE_TYPE := "01110110"; CONSTANT s360 : STATE_TYPE := "01110010"; CONSTANT s403 : STATE_TYPE := "01110011"; CONSTANT s406 : STATE_TYPE := "01110001"; CONSTANT s407 : STATE_TYPE := "01110000"; CONSTANT s409 : STATE_TYPE := "01010000"; CONSTANT s412 : STATE_TYPE := "01010001"; CONSTANT s413 : STATE_TYPE := "01010011"; CONSTANT s416 : STATE_TYPE := "01010010"; CONSTANT s418 : STATE_TYPE := "01010110"; CONSTANT s510 : STATE_TYPE := "01010111"; CONSTANT s553 : STATE_TYPE := "01010101"; CONSTANT s555 : STATE_TYPE := "01010100"; CONSTANT s558 : STATE_TYPE := "01011100"; CONSTANT s560 : STATE_TYPE := "01011101"; CONSTANT s561 : STATE_TYPE := "01011111"; CONSTANT s563 : STATE_TYPE := "01011110"; CONSTANT s564 : STATE_TYPE := "01011010"; CONSTANT s565 : STATE_TYPE := "01011011"; CONSTANT s566 : STATE_TYPE := "01011001"; CONSTANT s266 : STATE_TYPE := "01011000"; CONSTANT s301 : STATE_TYPE := "01001000"; CONSTANT s302 : STATE_TYPE := "01001001"; CONSTANT RES : STATE_TYPE := "01001011"; CONSTANT s511 : STATE_TYPE := "01001010"; CONSTANT s559 : STATE_TYPE := "01001110"; CONSTANT s562 : STATE_TYPE := "01001111"; CONSTANT s567 : STATE_TYPE := "01001101"; CONSTANT s568 : STATE_TYPE := "01001100"; CONSTANT s569 : STATE_TYPE := "01000100"; CONSTANT s570 : STATE_TYPE := "01000101"; CONSTANT s571 : STATE_TYPE := "01000111"; CONSTANT s572 : STATE_TYPE := "01000110"; CONSTANT s573 : STATE_TYPE := "01000010"; CONSTANT s574 : STATE_TYPE := "01000011"; CONSTANT s548 : STATE_TYPE := "01000001"; CONSTANT s551 : STATE_TYPE := "01000000"; CONSTANT s552 : STATE_TYPE := "11000000"; CONSTANT s575 : STATE_TYPE := "11000001"; CONSTANT s576 : STATE_TYPE := "11000011"; CONSTANT s577 : STATE_TYPE := "11000010"; CONSTANT s532 : STATE_TYPE := "11000110"; CONSTANT s533 : STATE_TYPE := "11000111"; CONSTANT s534 : STATE_TYPE := "11000101"; CONSTANT s535 : STATE_TYPE := "11000100"; CONSTANT s536 : STATE_TYPE := "11001100"; CONSTANT s537 : STATE_TYPE := "11001101"; -- Declare current and next state signals SIGNAL current_state : STATE_TYPE; SIGNAL next_state : STATE_TYPE; -- Declare any pre-registered internal signals SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 ); SIGNAL rd_o_cld : std_logic ; SIGNAL sync_o_cld : std_logic ; SIGNAL wr_n_o_cld : std_logic ; SIGNAL wr_o_cld : std_logic ; BEGIN ----------------------------------------------------------------- clocked_proc : PROCESS ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- BEGIN IF (rst_rst_n_i = '0') THEN current_state <= RES; -- Default Reset Values d_o_cld <= X"00"; rd_o_cld <= '0'; sync_o_cld <= '0'; wr_n_o_cld <= '1'; wr_o_cld <= '0'; reg_F <= "00000100"; reg_PC <= X"0000"; reg_PC1 <= X"0000"; reg_sel_pc_as <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_rb_in <= "00"; reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_sp_as <= '0'; reg_sel_sp_in <= '0'; sig_PC <= X"0000"; zw_PC <= X"0000"; zw_REG_ALU <= '0' & X"00"; zw_REG_NMI <= '0'; zw_REG_OP <= X"00"; zw_REG_sig_PC <= X"0000"; zw_b1 <= X"00"; zw_b2 <= X"00"; zw_b3 <= X"00"; zw_b4 <= X"00"; zw_so <= '0'; zw_w1 <= X"0000"; zw_w2 <= X"0000"; zw_w3 <= X"0000"; ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN current_state <= next_state; -- Default Assignment To Internals reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); reg_PC <= reg_PC; reg_PC1 <= reg_PC1; reg_sel_pc_as <= reg_sel_pc_as; reg_sel_pc_in <= reg_sel_pc_in; reg_sel_pc_val <= reg_sel_pc_val; reg_sel_rb_in <= reg_sel_rb_in; reg_sel_rb_out <= reg_sel_rb_out; reg_sel_reg <= reg_sel_reg; reg_sel_sp_as <= reg_sel_sp_as; reg_sel_sp_in <= reg_sel_sp_in; sig_PC <= sig_PC; zw_PC <= zw_PC; zw_REG_ALU <= zw_REG_ALU; zw_REG_NMI <= zw_REG_NMI or nmi_i; zw_REG_OP <= zw_REG_OP; zw_REG_sig_PC <= zw_REG_sig_PC; zw_b1 <= zw_b1; zw_b2 <= zw_b2; zw_b3 <= zw_b3; zw_b4 <= zw_b4; zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); zw_w1 <= zw_w1; zw_w2 <= zw_w2; zw_w3 <= zw_w3; d_o_cld <= sig_D_OUT; rd_o_cld <= sig_RD; sync_o_cld <= sig_SYNC; wr_n_o_cld <= sig_RWn; wr_o_cld <= sig_WR; -- Combined Actions CASE current_state IS WHEN FETCH => zw_REG_OP <= d_i; IF ((nmi_i = '1') AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; zw_REG_NMI <= '0'; ELSIF ((irq_n_i = '0' and reg_F(2) = '0') AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; zw_b1(0) <= reg_F(7); ELSIF ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; zw_b3 <= adr_nxt_pc_i (15 downto 8); ELSIF ((d_i = X"24" or d_i = X"2C") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") AND (rdy_i = '1')) THEN zw_b4 <= X"FF"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "10"; reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; ELSIF ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") AND (rdy_i = '1')) THEN zw_b4 <= X"01"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "10"; reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; ELSIF ((d_i = X"4C" or d_i = X"6C") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1") AND (rdy_i = '1')) THEN reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") AND (rdy_i = '1')) THEN reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") AND (rdy_i = '1')) THEN reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1") AND (rdy_i = '1')) THEN sig_PC <= adr_nxt_pc_i; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; zw_b1(0) <= reg_F(7); ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN ELSIF ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"86" or d_i = X"96" or d_i = X"8E") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"84" or d_i = X"94" or d_i = X"8C") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "01"; reg_sel_rb_in <= "00"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "00"; reg_sel_reg <= "10"; reg_sel_rb_in <= "00"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "10"; reg_sel_reg <= "00"; reg_sel_rb_in <= "01"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; reg_sel_reg <= "00"; reg_sel_rb_in <= "10"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN reg_sel_rb_out <= "01"; reg_sel_reg <= "11"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; END IF; WHEN s1 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s2 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(0) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s5 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(3) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s3 => sig_PC <= adr_pc_i; IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(2) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s4 => IF (rdy_i = '1' and zw_REG_OP = X"9A") THEN sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"BA") THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s12 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(0) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s16 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(3) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s17 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(2) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s24 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(6) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s25 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s271 => IF (rdy_i = '1' and zw_REG_OP = X"4C") THEN sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; zw_b1 <= d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"6C") THEN sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; zw_b1 <= d_i; END IF; WHEN s273 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; zw_b2 <= d_i; END IF; WHEN s304 => IF (rdy_i = '1') THEN sig_PC <= zw_b2 & adr_pc_i(7 downto 0); reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; zw_b1 <= d_i; END IF; WHEN s307 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s177 => IF (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"84")) THEN sig_PC <= X"00" & d_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"94")) THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"8C")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"9D") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"99") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"91") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"81") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"96") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; END IF; WHEN s180 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s181 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; END IF; WHEN s182 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s183 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s184 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s185 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s186 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s187 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s188 => IF (rdy_i = '1') THEN sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; END IF; WHEN s189 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s190 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s191 => sig_PC <= zw_b3 & zw_b1; WHEN s192 => sig_PC <= d_i & zw_b1; WHEN s193 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s377 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s381 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s378 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s382 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s383 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s384 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s385 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s386 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F <= d_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s387 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s388 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s389 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; reg_F <= d_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; END IF; WHEN s391 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; zw_b1 <= d_i; END IF; WHEN s392 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s390 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s393 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s394 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; zw_b1 <= d_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; END IF; WHEN s395 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s396 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s397 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; zw_b1 <= d_i; END IF; WHEN s399 => sig_PC <= adr_sp_i; WHEN s400 => sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; WHEN s401 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1 (7 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s526 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s527 => sig_PC <= adr_sp_i; WHEN s528 => sig_PC <= adr_sp_i; WHEN s529 => sig_PC <= X"FFFE"; WHEN s530 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; reg_F(2) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s531 => IF (rdy_i = '1') THEN sig_PC <= X"FFFF"; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; zw_b1 <= d_i; END IF; WHEN s544 => sig_PC <= adr_sp_i; WHEN s545 => sig_PC <= adr_sp_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; WHEN s546 => sig_PC <= adr_pc_i; WHEN s547 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; zw_w1 (7 downto 0) <= d_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; END IF; WHEN s549 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_w1 (7 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s550 => sig_PC <= adr_sp_i; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; WHEN s404 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(7); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s556 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s557 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(7); reg_F(0) <= q_a_i(7); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s579 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s201 => IF (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN sig_PC <= X"00" & d_i; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"B6") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; END IF; WHEN s202 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s210 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s211 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s215 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; END IF; WHEN s217 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s218 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s222 => IF (rdy_i = '1') THEN sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; END IF; WHEN s223 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s224 => IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s225 => IF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' AND zw_b2(0) = '0') THEN sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= zw_b3 & zw_b1; END IF; WHEN s226 => IF (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) THEN sig_PC <= X"00" & d_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; END IF; WHEN s243 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s244 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s247 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s344 => IF (rdy_i = '1') THEN sig_PC <= zw_b3 & zw_b1; END IF; WHEN s343 => IF (rdy_i = '1') THEN zw_b1 <= d_alu_i; END IF; WHEN s251 => sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s351 => IF (rdy_i = '1' and zw_REG_OP = X"24") THEN sig_PC <= X"00" & d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"2C") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; END IF; WHEN s361 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= d_i(7); reg_F(6) <= d_i(6); reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s360 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s403 => IF (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46")) THEN sig_PC <= X"00" & d_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E")) THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; END IF; WHEN s406 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s407 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s409 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s412 => IF (rdy_i = '1') THEN sig_PC <= zw_b3 & zw_b1; END IF; WHEN s416 => IF (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) THEN zw_b1 <= d_i(6 downto 0) & '0'; zw_b2(0) <= d_i(7); ELSIF (rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) THEN zw_b1 <= '0' & d_i(7 downto 1); zw_b2(0) <= d_i(0); ELSIF (rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) THEN zw_b1 <= d_i(6 downto 0) & reg_F(0); zw_b2(0) <= d_i(7); ELSIF (rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) THEN zw_b1 <= reg_F(0) & d_i(7 downto 1); zw_b2(0) <= d_i(0); END IF; WHEN s418 => sig_PC <= adr_pc_i; reg_F(0) <= zw_b2(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s510 => IF (rdy_i = '1' and zw_REG_OP = X"65") THEN sig_PC <= X"00" & d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"75") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"6D") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"7D") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"79") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"71") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"61") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU4(4); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s553 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s555 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s558 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; END IF; WHEN s560 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s561 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s563 => IF (rdy_i = '1') THEN sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; END IF; WHEN s564 => IF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU4(4); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= zw_b3 & zw_b1; END IF; WHEN s565 => IF (rdy_i = '1' and reg_F(3) = '0') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and reg_F(3) = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU4(4); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s566 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s266 => IF (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "10"; zw_b2 <= d_i; END IF; WHEN s301 => IF (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); END IF; WHEN s302 => IF (rdy_i = '1') THEN sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN RES => reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_pc_as <= '0'; sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; WHEN s511 => IF (rdy_i = '1' and zw_REG_OP = X"E5") THEN sig_PC <= X"00" & d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"F5") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"ED") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"FD") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"F9") THEN sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"F1") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"E1") THEN sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') THEN sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU2(4); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s559 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; END IF; WHEN s562 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s567 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s568 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; END IF; WHEN s569 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s570 => IF (rdy_i = '1') THEN sig_PC <= X"00" & zw_b1; END IF; WHEN s571 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; END IF; WHEN s572 => IF (rdy_i = '1') THEN sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; END IF; WHEN s573 => IF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU2(4); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1') THEN sig_PC <= zw_b3 & zw_b1; END IF; WHEN s574 => IF (rdy_i = '1' and reg_F(3) = '0') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; ELSIF (rdy_i = '1' and reg_F(3) = '1') THEN sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= zw_b1(0) XOR zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU2(4); reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s548 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s551 => sig_PC <= adr_sp_i; WHEN s552 => sig_PC <= adr_sp_i; WHEN s575 => IF (rdy_i = '1') THEN sig_PC <= X"FFFF"; zw_b1 <= d_i; END IF; WHEN s576 => sig_PC <= X"FFFE"; WHEN s577 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; reg_F(2) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN s532 => IF (rdy_i = '1') THEN sig_PC <= adr_sp_i; END IF; WHEN s533 => sig_PC <= adr_sp_i; WHEN s534 => sig_PC <= adr_sp_i; WHEN s535 => IF (rdy_i = '1') THEN sig_PC <= X"FFFB"; reg_sel_pc_in <= '1'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "11"; zw_b1 <= d_i; END IF; WHEN s536 => sig_PC <= X"FFFA"; WHEN s537 => IF (rdy_i = '1') THEN sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_as <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; END IF; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS clocked_proc; ----------------------------------------------------------------- nextstate_proc : PROCESS ( adr_nxt_pc_i, current_state, d_i, irq_n_i, nmi_i, rdy_i, reg_F, zw_REG_OP, zw_b2, zw_b3 ) ----------------------------------------------------------------- BEGIN CASE current_state IS WHEN FETCH => IF ((nmi_i = '1') AND (rdy_i = '1')) THEN next_state <= s532; ELSIF ((irq_n_i = '0' and reg_F(2) = '0') AND (rdy_i = '1')) THEN next_state <= s548; ELSIF ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71") AND (rdy_i = '1')) THEN next_state <= s510; ELSIF ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E") AND (rdy_i = '1')) THEN next_state <= s403; ELSIF ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70") AND (rdy_i = '1')) THEN next_state <= s266; ELSIF ((d_i = X"24" or d_i = X"2C") AND (rdy_i = '1')) THEN next_state <= s351; ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN next_state <= s526; ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN next_state <= s12; ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN next_state <= s16; ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN next_state <= s17; ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN next_state <= s24; ELSIF ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") AND (rdy_i = '1')) THEN next_state <= s201; ELSIF ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") AND (rdy_i = '1')) THEN next_state <= s201; ELSIF ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") AND (rdy_i = '1')) THEN next_state <= s226; ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN next_state <= s25; ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN next_state <= s25; ELSIF ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1") AND (rdy_i = '1')) THEN next_state <= s201; ELSIF ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") AND (rdy_i = '1')) THEN next_state <= s226; ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN next_state <= s25; ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN next_state <= s25; ELSIF ((d_i = X"4C" or d_i = X"6C") AND (rdy_i = '1')) THEN next_state <= s271; ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN next_state <= s397; ELSIF ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1") AND (rdy_i = '1')) THEN next_state <= s201; ELSIF ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") AND (rdy_i = '1')) THEN next_state <= s201; ELSIF ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") AND (rdy_i = '1')) THEN next_state <= s201; ELSIF ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") AND (rdy_i = '1')) THEN next_state <= s403; ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN next_state <= s1; ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN next_state <= s377; ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN next_state <= s378; ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN next_state <= s379; ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN next_state <= s380; ELSIF ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") AND (rdy_i = '1')) THEN next_state <= s403; ELSIF ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") AND (rdy_i = '1')) THEN next_state <= s403; ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN next_state <= s387; ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN next_state <= s390; ELSIF ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1") AND (rdy_i = '1')) THEN next_state <= s511; ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN next_state <= s2; ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN next_state <= s5; ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN next_state <= s3; ELSIF ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91") AND (rdy_i = '1')) THEN next_state <= s177; ELSIF ((d_i = X"86" or d_i = X"96" or d_i = X"8E") AND (rdy_i = '1')) THEN next_state <= s177; ELSIF ((d_i = X"84" or d_i = X"94" or d_i = X"8C") AND (rdy_i = '1')) THEN next_state <= s177; ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN next_state <= s4; ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN next_state <= s404; ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN next_state <= s556; ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN next_state <= s557; ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN next_state <= s579; ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN next_state <= s4; ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN next_state <= s4; ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN next_state <= s4; ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN next_state <= s4; ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN next_state <= s4; ELSIF (rdy_i = '1') THEN next_state <= s1; ELSE next_state <= FETCH; END IF; WHEN s1 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s1; END IF; WHEN s2 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s2; END IF; WHEN s5 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s5; END IF; WHEN s3 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s3; END IF; WHEN s4 => IF (rdy_i = '1' and zw_REG_OP = X"9A") THEN next_state <= FETCH; ELSIF (rdy_i = '1' and zw_REG_OP = X"BA") THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s4; END IF; WHEN s12 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s12; END IF; WHEN s16 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s16; END IF; WHEN s17 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s17; END IF; WHEN s24 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s24; END IF; WHEN s25 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s25; END IF; WHEN s271 => IF (rdy_i = '1' and zw_REG_OP = X"4C") THEN next_state <= s307; ELSIF (rdy_i = '1' and zw_REG_OP = X"6C") THEN next_state <= s273; ELSE next_state <= s271; END IF; WHEN s273 => IF (rdy_i = '1') THEN next_state <= s304; ELSE next_state <= s273; END IF; WHEN s304 => IF (rdy_i = '1') THEN next_state <= s307; ELSE next_state <= s304; END IF; WHEN s307 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s307; END IF; WHEN s177 => IF (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"84")) THEN next_state <= s184; ELSIF (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"94")) THEN next_state <= s185; ELSIF (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"8C")) THEN next_state <= s183; ELSIF (rdy_i = '1' and zw_REG_OP = X"9D") THEN next_state <= s182; ELSIF (rdy_i = '1' and zw_REG_OP = X"99") THEN next_state <= s180; ELSIF (rdy_i = '1' and zw_REG_OP = X"91") THEN next_state <= s181; ELSIF (rdy_i = '1' and zw_REG_OP = X"81") THEN next_state <= s186; ELSIF (rdy_i = '1' and zw_REG_OP = X"96") THEN next_state <= s185; ELSE next_state <= s177; END IF; WHEN s180 => IF (rdy_i = '1') THEN next_state <= s191; ELSE next_state <= s180; END IF; WHEN s181 => IF (rdy_i = '1') THEN next_state <= s189; ELSE next_state <= s181; END IF; WHEN s182 => IF (rdy_i = '1') THEN next_state <= s191; ELSE next_state <= s182; END IF; WHEN s183 => IF (rdy_i = '1') THEN next_state <= s187; ELSE next_state <= s183; END IF; WHEN s184 => next_state <= FETCH; WHEN s185 => IF (rdy_i = '1') THEN next_state <= s190; ELSE next_state <= s185; END IF; WHEN s186 => IF (rdy_i = '1') THEN next_state <= s188; ELSE next_state <= s186; END IF; WHEN s187 => next_state <= FETCH; WHEN s188 => IF (rdy_i = '1') THEN next_state <= s192; ELSE next_state <= s188; END IF; WHEN s189 => IF (rdy_i = '1') THEN next_state <= s191; ELSE next_state <= s189; END IF; WHEN s190 => next_state <= FETCH; WHEN s191 => next_state <= s193; WHEN s192 => next_state <= s193; WHEN s193 => next_state <= FETCH; WHEN s377 => IF (rdy_i = '1') THEN next_state <= s381; ELSE next_state <= s377; END IF; WHEN s381 => next_state <= FETCH; WHEN s378 => IF (rdy_i = '1') THEN next_state <= s382; ELSE next_state <= s378; END IF; WHEN s382 => next_state <= FETCH; WHEN s379 => IF (rdy_i = '1') THEN next_state <= s383; ELSE next_state <= s379; END IF; WHEN s383 => IF (rdy_i = '1') THEN next_state <= s384; ELSE next_state <= s383; END IF; WHEN s384 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s384; END IF; WHEN s380 => IF (rdy_i = '1') THEN next_state <= s385; ELSE next_state <= s380; END IF; WHEN s385 => IF (rdy_i = '1') THEN next_state <= s386; ELSE next_state <= s385; END IF; WHEN s386 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s386; END IF; WHEN s387 => IF (rdy_i = '1') THEN next_state <= s388; ELSE next_state <= s387; END IF; WHEN s388 => IF (rdy_i = '1') THEN next_state <= s389; ELSE next_state <= s388; END IF; WHEN s389 => IF (rdy_i = '1') THEN next_state <= s391; ELSE next_state <= s389; END IF; WHEN s391 => IF (rdy_i = '1') THEN next_state <= s392; ELSE next_state <= s391; END IF; WHEN s392 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s392; END IF; WHEN s390 => IF (rdy_i = '1') THEN next_state <= s393; ELSE next_state <= s390; END IF; WHEN s393 => IF (rdy_i = '1') THEN next_state <= s394; ELSE next_state <= s393; END IF; WHEN s394 => IF (rdy_i = '1') THEN next_state <= s395; ELSE next_state <= s394; END IF; WHEN s395 => IF (rdy_i = '1') THEN next_state <= s396; ELSE next_state <= s395; END IF; WHEN s396 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s396; END IF; WHEN s397 => IF (rdy_i = '1') THEN next_state <= s398; ELSE next_state <= s397; END IF; WHEN s398 => IF (rdy_i = '1') THEN next_state <= s399; ELSE next_state <= s398; END IF; WHEN s399 => next_state <= s400; WHEN s400 => next_state <= s401; WHEN s401 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s401; END IF; WHEN s526 => IF (rdy_i = '1') THEN next_state <= s527; ELSE next_state <= s526; END IF; WHEN s527 => next_state <= s528; WHEN s528 => next_state <= s529; WHEN s529 => next_state <= s531; WHEN s530 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s530; END IF; WHEN s531 => IF (rdy_i = '1') THEN next_state <= s530; ELSE next_state <= s531; END IF; WHEN s544 => next_state <= s550; WHEN s545 => next_state <= s546; WHEN s546 => next_state <= s547; WHEN s547 => IF (rdy_i = '1') THEN next_state <= s549; ELSE next_state <= s547; END IF; WHEN s549 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s549; END IF; WHEN s550 => next_state <= s545; WHEN s404 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s404; END IF; WHEN s556 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s556; END IF; WHEN s557 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s557; END IF; WHEN s579 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s579; END IF; WHEN s201 => IF (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN next_state <= s224; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN next_state <= FETCH; ELSIF (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN next_state <= FETCH; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) THEN next_state <= s217; ELSIF (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) THEN next_state <= s202; ELSIF (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) THEN next_state <= s210; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) THEN next_state <= s211; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) THEN next_state <= s215; ELSIF (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) THEN next_state <= s218; ELSIF (rdy_i = '1' and zw_REG_OP = X"B6") THEN next_state <= s217; ELSE next_state <= s201; END IF; WHEN s202 => IF (rdy_i = '1') THEN next_state <= s224; ELSE next_state <= s202; END IF; WHEN s210 => IF (rdy_i = '1') THEN next_state <= s225; ELSE next_state <= s210; END IF; WHEN s211 => IF (rdy_i = '1') THEN next_state <= s225; ELSE next_state <= s211; END IF; WHEN s215 => IF (rdy_i = '1') THEN next_state <= s223; ELSE next_state <= s215; END IF; WHEN s217 => IF (rdy_i = '1') THEN next_state <= s224; ELSE next_state <= s217; END IF; WHEN s218 => IF (rdy_i = '1') THEN next_state <= s222; ELSE next_state <= s218; END IF; WHEN s222 => IF (rdy_i = '1') THEN next_state <= s202; ELSE next_state <= s222; END IF; WHEN s223 => IF (rdy_i = '1') THEN next_state <= s225; ELSE next_state <= s223; END IF; WHEN s224 => IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s224; END IF; WHEN s225 => IF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN next_state <= FETCH; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN next_state <= FETCH; ELSIF (rdy_i = '1' AND zw_b2(0) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= s224; ELSE next_state <= s225; END IF; WHEN s226 => IF (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) THEN next_state <= s343; ELSIF (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) THEN next_state <= s247; ELSIF (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) THEN next_state <= s243; ELSIF (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) THEN next_state <= s244; ELSE next_state <= s226; END IF; WHEN s243 => IF (rdy_i = '1') THEN next_state <= s343; ELSE next_state <= s243; END IF; WHEN s244 => IF (rdy_i = '1') THEN next_state <= s344; ELSE next_state <= s244; END IF; WHEN s247 => IF (rdy_i = '1') THEN next_state <= s343; ELSE next_state <= s247; END IF; WHEN s344 => IF (rdy_i = '1') THEN next_state <= s343; ELSE next_state <= s344; END IF; WHEN s343 => IF (rdy_i = '1') THEN next_state <= s250; ELSE next_state <= s343; END IF; WHEN s250 => IF (rdy_i = '1') THEN next_state <= s251; ELSE next_state <= s250; END IF; WHEN s251 => next_state <= FETCH; WHEN s351 => IF (rdy_i = '1' and zw_REG_OP = X"24") THEN next_state <= s361; ELSIF (rdy_i = '1' and zw_REG_OP = X"2C") THEN next_state <= s360; ELSE next_state <= s351; END IF; WHEN s361 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s361; END IF; WHEN s360 => IF (rdy_i = '1') THEN next_state <= s361; ELSE next_state <= s360; END IF; WHEN s403 => IF (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) THEN next_state <= s407; ELSIF (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46")) THEN next_state <= s413; ELSIF (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) THEN next_state <= s409; ELSIF (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E")) THEN next_state <= s406; ELSE next_state <= s403; END IF; WHEN s406 => IF (rdy_i = '1') THEN next_state <= s413; ELSE next_state <= s406; END IF; WHEN s407 => IF (rdy_i = '1') THEN next_state <= s412; ELSE next_state <= s407; END IF; WHEN s409 => IF (rdy_i = '1') THEN next_state <= s413; ELSE next_state <= s409; END IF; WHEN s412 => IF (rdy_i = '1') THEN next_state <= s413; ELSE next_state <= s412; END IF; WHEN s413 => IF (rdy_i = '1') THEN next_state <= s416; ELSE next_state <= s413; END IF; WHEN s416 => IF (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) THEN next_state <= s418; ELSIF (rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) THEN next_state <= s418; ELSIF (rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) THEN next_state <= s418; ELSIF (rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) THEN next_state <= s418; ELSE next_state <= s416; END IF; WHEN s418 => next_state <= FETCH; WHEN s510 => IF (rdy_i = '1' and zw_REG_OP = X"65") THEN next_state <= s565; ELSIF (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1' and zw_REG_OP = X"75") THEN next_state <= s560; ELSIF (rdy_i = '1' and zw_REG_OP = X"6D") THEN next_state <= s553; ELSIF (rdy_i = '1' and zw_REG_OP = X"7D") THEN next_state <= s555; ELSIF (rdy_i = '1' and zw_REG_OP = X"79") THEN next_state <= s555; ELSIF (rdy_i = '1' and zw_REG_OP = X"71") THEN next_state <= s558; ELSIF (rdy_i = '1' and zw_REG_OP = X"61") THEN next_state <= s561; ELSIF (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') THEN next_state <= FETCH; ELSE next_state <= s510; END IF; WHEN s553 => IF (rdy_i = '1') THEN next_state <= s565; ELSE next_state <= s553; END IF; WHEN s555 => IF (rdy_i = '1') THEN next_state <= s564; ELSE next_state <= s555; END IF; WHEN s558 => IF (rdy_i = '1') THEN next_state <= s566; ELSE next_state <= s558; END IF; WHEN s560 => IF (rdy_i = '1') THEN next_state <= s565; ELSE next_state <= s560; END IF; WHEN s561 => IF (rdy_i = '1') THEN next_state <= s563; ELSE next_state <= s561; END IF; WHEN s563 => IF (rdy_i = '1') THEN next_state <= s553; ELSE next_state <= s563; END IF; WHEN s564 => IF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= s565; ELSE next_state <= s564; END IF; WHEN s565 => IF (rdy_i = '1' and reg_F(3) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1' and reg_F(3) = '1') THEN next_state <= FETCH; ELSE next_state <= s565; END IF; WHEN s566 => IF (rdy_i = '1') THEN next_state <= s564; ELSE next_state <= s566; END IF; WHEN s266 => IF (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= s301; ELSE next_state <= s266; END IF; WHEN s301 => IF (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= s302; ELSE next_state <= s301; END IF; WHEN s302 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s302; END IF; WHEN RES => next_state <= s544; WHEN s511 => IF (rdy_i = '1' and zw_REG_OP = X"E5") THEN next_state <= s574; ELSIF (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1' and zw_REG_OP = X"F5") THEN next_state <= s569; ELSIF (rdy_i = '1' and zw_REG_OP = X"ED") THEN next_state <= s559; ELSIF (rdy_i = '1' and zw_REG_OP = X"FD") THEN next_state <= s562; ELSIF (rdy_i = '1' and zw_REG_OP = X"F9") THEN next_state <= s567; ELSIF (rdy_i = '1' and zw_REG_OP = X"F1") THEN next_state <= s568; ELSIF (rdy_i = '1' and zw_REG_OP = X"E1") THEN next_state <= s570; ELSIF (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') THEN next_state <= FETCH; ELSE next_state <= s511; END IF; WHEN s559 => IF (rdy_i = '1') THEN next_state <= s574; ELSE next_state <= s559; END IF; WHEN s562 => IF (rdy_i = '1') THEN next_state <= s573; ELSE next_state <= s562; END IF; WHEN s567 => IF (rdy_i = '1') THEN next_state <= s573; ELSE next_state <= s567; END IF; WHEN s568 => IF (rdy_i = '1') THEN next_state <= s571; ELSE next_state <= s568; END IF; WHEN s569 => IF (rdy_i = '1') THEN next_state <= s574; ELSE next_state <= s569; END IF; WHEN s570 => IF (rdy_i = '1') THEN next_state <= s572; ELSE next_state <= s570; END IF; WHEN s571 => IF (rdy_i = '1') THEN next_state <= s573; ELSE next_state <= s571; END IF; WHEN s572 => IF (rdy_i = '1') THEN next_state <= s559; ELSE next_state <= s572; END IF; WHEN s573 => IF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') THEN next_state <= FETCH; ELSIF (rdy_i = '1') THEN next_state <= s574; ELSE next_state <= s573; END IF; WHEN s574 => IF (rdy_i = '1' and reg_F(3) = '0') THEN next_state <= FETCH; ELSIF (rdy_i = '1' and reg_F(3) = '1') THEN next_state <= FETCH; ELSE next_state <= s574; END IF; WHEN s548 => IF (rdy_i = '1') THEN next_state <= s551; ELSE next_state <= s548; END IF; WHEN s551 => next_state <= s552; WHEN s552 => next_state <= s576; WHEN s575 => IF (rdy_i = '1') THEN next_state <= s577; ELSE next_state <= s575; END IF; WHEN s576 => next_state <= s575; WHEN s577 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s577; END IF; WHEN s532 => IF (rdy_i = '1') THEN next_state <= s533; ELSE next_state <= s532; END IF; WHEN s533 => next_state <= s534; WHEN s534 => next_state <= s536; WHEN s535 => IF (rdy_i = '1') THEN next_state <= s537; ELSE next_state <= s535; END IF; WHEN s536 => next_state <= s535; WHEN s537 => IF (rdy_i = '1') THEN next_state <= FETCH; ELSE next_state <= s537; END IF; WHEN OTHERS => next_state <= RES; END CASE; END PROCESS nextstate_proc; ----------------------------------------------------------------- output_proc : PROCESS ( adr_nxt_pc_i, adr_pc_i, adr_sp_i, current_state, d_alu_i, d_i, d_regs_out_i, irq_n_i, nmi_i, q_a_i, q_x_i, q_y_i, rdy_i, reg_F, reg_sel_pc_as, reg_sel_pc_in, reg_sel_pc_val, reg_sel_rb_in, reg_sel_rb_out, reg_sel_reg, reg_sel_sp_as, reg_sel_sp_in, sig_PC, zw_ALU, zw_ALU1, zw_ALU2, zw_ALU3, zw_ALU4, zw_ALU5, zw_ALU6, zw_REG_OP, zw_b1, zw_b2, zw_b3, zw_b4, zw_w1 ) ----------------------------------------------------------------- BEGIN -- Default Assignment a_o <= sig_PC; adr_o <= X"0000"; ch_a_o <= X"00"; ch_b_o <= X"00"; d_regs_in_o <= X"00"; fetch_o <= '0'; ld_o <= "00"; ld_pc_o <= '0'; ld_sp_o <= '0'; load_regs_o <= '0'; offset_o <= X"0000"; sel_pc_as_o <= reg_sel_pc_as; sel_pc_in_o <= reg_sel_pc_in; sel_pc_val_o <= reg_sel_pc_val; sel_rb_in_o <= reg_sel_rb_in; sel_rb_out_o <= reg_sel_rb_out; sel_reg_o <= reg_sel_reg; sel_sp_as_o <= reg_sel_sp_as; sel_sp_in_o <= reg_sel_sp_in; -- Default Assignment To Internals sig_D_OUT <= X"00"; sig_RD <= '1'; sig_RWn <= '1'; sig_SYNC <= '0'; sig_WR <= '0'; zw_ALU <= '0' & X"00"; zw_ALU1 <= '0' & X"00"; zw_ALU2 <= '0' & X"00"; zw_ALU3 <= '0' & X"00"; zw_ALU4 <= '0' & X"00"; zw_ALU5 <= '0' & X"00"; zw_ALU6 <= '0' & X"00"; -- Combined Actions CASE current_state IS WHEN FETCH => sig_RWn <= '1'; sig_RD <= '1'; sig_SYNC <= NOT (rdy_i); IF ((nmi_i = '1') AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((irq_n_i = '0' and reg_F(2) = '0') AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"24" or d_i = X"2C") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"4C" or d_i = X"6C") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"86" or d_i = X"96" or d_i = X"8E") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"84" or d_i = X"94" or d_i = X"8C") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s1 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s2 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s5 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s3 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s4 => IF (rdy_i = '1' and zw_REG_OP = X"9A") THEN adr_o <= X"01" & d_regs_out_i; ld_o <= "11"; ld_sp_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"BA") THEN d_regs_in_o <= adr_sp_i (7 downto 0); ch_a_o <= adr_sp_i (7 downto 0); ch_b_o <= X"00"; load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1') THEN ch_a_o <= d_regs_out_i; ch_b_o <= X"00"; load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s12 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s16 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s17 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s24 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s25 => IF (rdy_i = '1') THEN d_regs_in_o <= d_alu_i; ch_a_o <= d_regs_out_i; ch_b_o <= zw_b4; load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s273 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s307 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s177 => IF (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"84")) THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"94")) THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"8C")) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"9D") THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"99") THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"91") THEN ch_a_o <= d_i; ch_b_o <= X"01"; ELSIF (rdy_i = '1' and zw_REG_OP = X"81") THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"96") THEN ch_a_o <= d_i; ch_b_o <= q_y_i; END IF; WHEN s180 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s181 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= q_y_i; END IF; WHEN s182 => sig_RWn <= '1'; sig_RD <= '1'; IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s183 => IF (rdy_i = '1') THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s184 => sig_SYNC <= '1'; fetch_o <= '1'; WHEN s185 => IF (rdy_i = '1') THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s187 => sig_SYNC <= '1'; fetch_o <= '1'; WHEN s188 => IF (rdy_i = '1') THEN ch_a_o <= zw_b1; ch_b_o <= X"01"; END IF; WHEN s189 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s190 => sig_SYNC <= '1'; fetch_o <= '1'; WHEN s191 => sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; WHEN s192 => sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; WHEN s193 => sig_SYNC <= '1'; fetch_o <= '1'; WHEN s377 => IF (rdy_i = '1') THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= q_a_i; ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s381 => sig_SYNC <= '1'; fetch_o <= '1'; WHEN s378 => IF (rdy_i = '1') THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F; ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s382 => sig_SYNC <= '1'; fetch_o <= '1'; WHEN s379 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s384 => IF (rdy_i = '1') THEN d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s380 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s386 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s387 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s388 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s389 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s392 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s390 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s393 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; END IF; WHEN s395 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s396 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s397 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; ld_pc_o <= '1'; END IF; WHEN s398 => IF (rdy_i = '1') THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); END IF; WHEN s399 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); WHEN s401 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s526 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; ld_pc_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); END IF; WHEN s527 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); WHEN s528 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F OR X"10"; WHEN s530 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s544 => ld_o <= "11"; ld_sp_o <= '1'; WHEN s545 => adr_o <= X"FFFB"; ld_o <= "11"; ld_pc_o <= '1'; WHEN s546 => ld_o <= "11"; ld_pc_o <= '1'; WHEN s549 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_w1 (7 downto 0); ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s550 => ld_o <= "11"; ld_sp_o <= '1'; WHEN s404 => IF (rdy_i = '1') THEN ch_a_o <= q_a_i (6 downto 0) & '0'; ch_b_o <= X"00"; d_regs_in_o <= q_a_i (6 downto 0) & '0'; load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s556 => IF (rdy_i = '1') THEN ch_a_o <= '0' & q_a_i (7 downto 1); ch_b_o <= X"00"; d_regs_in_o <= '0' & q_a_i (7 downto 1); load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s557 => IF (rdy_i = '1') THEN ch_a_o <= q_a_i (6 downto 0) & reg_F(0); ch_b_o <= X"00"; d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0); load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s579 => IF (rdy_i = '1') THEN ch_a_o <= reg_F(0) & q_a_i (7 downto 1); ch_b_o <= X"00"; d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1); load_regs_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s201 => IF (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN ld_o <= "11"; ld_pc_o <= '1'; zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) THEN ch_a_o <= d_i; ch_b_o <= X"01"; ELSIF (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"B6") THEN ch_a_o <= d_i; ch_b_o <= q_y_i; END IF; WHEN s202 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s210 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s211 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s215 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= q_y_i; END IF; WHEN s217 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s222 => IF (rdy_i = '1') THEN ch_a_o <= zw_b1; ch_b_o <= X"01"; END IF; WHEN s223 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s224 => IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1') THEN d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s225 => IF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF ((rdy_i = '1' AND zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' AND zw_b2(0) = '0') THEN d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s226 => IF (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; END IF; WHEN s243 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s244 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s247 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s343 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= zw_b4; END IF; WHEN s250 => IF (rdy_i = '1') THEN sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b1; END IF; WHEN s251 => ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; WHEN s351 => IF (rdy_i = '1' and zw_REG_OP = X"24") THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"2C") THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s361 => IF (rdy_i = '1') THEN ch_a_o <= q_a_i AND d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s360 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s403 => IF (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46")) THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E")) THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s406 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s407 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s409 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s416 => IF (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) THEN sig_D_OUT <= d_i(6 downto 0) & '0'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) THEN sig_D_OUT <= '0' & d_i(7 downto 1); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) THEN sig_D_OUT <= d_i(6 downto 0) & reg_F(0); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; ELSIF (rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) THEN sig_D_OUT <= reg_F(0) & d_i(7 downto 1); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; END IF; WHEN s418 => ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; fetch_o <= '1'; WHEN s510 => IF (rdy_i = '1' and zw_REG_OP = X"65") THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"75") THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"6D") THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"7D") THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"79") THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"71") THEN ch_a_o <= d_i; ch_b_o <= X"01"; ELSIF (rdy_i = '1' and zw_REG_OP = X"61") THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s553 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s555 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s558 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= q_y_i; END IF; WHEN s560 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s563 => IF (rdy_i = '1') THEN ch_a_o <= zw_b1; ch_b_o <= X"01"; END IF; WHEN s564 => IF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s565 => IF (rdy_i = '1' and reg_F(3) = '0') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and reg_F(3) = '1') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s566 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s266 => IF (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s301 => IF (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1') THEN offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s302 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN RES => sig_RWn <= '1'; sig_RD <= '1'; ld_o <= "11"; ld_pc_o <= '1'; ld_sp_o <= '1'; sig_RWn <= '1'; sig_RD <= '1'; WHEN s511 => IF (rdy_i = '1' and zw_REG_OP = X"E5") THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"F5") THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"ED") THEN ld_o <= "11"; ld_pc_o <= '1'; ELSIF (rdy_i = '1' and zw_REG_OP = X"FD") THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"F9") THEN ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"F1") THEN ch_a_o <= d_i; ch_b_o <= X"01"; ELSIF (rdy_i = '1' and zw_REG_OP = X"E1") THEN ch_a_o <= d_i; ch_b_o <= q_x_i; ELSIF (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned ((zw_ALU6(8 downto 5))); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned ((zw_ALU5(8 downto 5))); zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s559 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s562 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s567 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s568 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= q_y_i; END IF; WHEN s569 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s571 => IF (rdy_i = '1') THEN ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; ld_pc_o <= '1'; END IF; WHEN s572 => IF (rdy_i = '1') THEN ch_a_o <= zw_b1; ch_b_o <= X"01"; END IF; WHEN s573 => IF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned ((zw_ALU6(8 downto 5))); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned ((zw_ALU5(8 downto 5))); zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s574 => IF (rdy_i = '1' and reg_F(3) = '0') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; ELSIF (rdy_i = '1' and reg_F(3) = '1') THEN d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned ((zw_ALU6(8 downto 5))); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned ((zw_ALU5(8 downto 5))); zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0); sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s548 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; ld_pc_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); END IF; WHEN s551 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); WHEN s552 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F; WHEN s577 => IF (rdy_i = '1') THEN sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN s532 => IF (rdy_i = '1') THEN ld_o <= "11"; ld_sp_o <= '1'; ld_pc_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); END IF; WHEN s533 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); WHEN s534 => ld_o <= "11"; ld_sp_o <= '1'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F; WHEN s537 => IF (rdy_i = '1') THEN adr_o <= d_i & zw_b1; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; fetch_o <= '1'; END IF; WHEN OTHERS => NULL; END CASE; END PROCESS output_proc; -- Concurrent Statements -- Clocked output assignments d_o <= d_o_cld; rd_o <= rd_o_cld; sync_o <= sync_o_cld; wr_n_o <= wr_n_o_cld; wr_o <= wr_o_cld; END fsm;
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