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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity fsm_execution_unit is port( adr_nxt_pc_i : in std_logic_vector (15 downto 0); adr_pc_i : in std_logic_vector (15 downto 0); adr_sp_i : in std_logic_vector (15 downto 0); clk_clk_i : in std_logic; d_alu_i : in std_logic_vector ( 7 downto 0 ); d_alu_prio_i : in std_logic_vector (7 downto 0); d_i : in std_logic_vector ( 7 downto 0 ); d_regs_out_i : in std_logic_vector ( 7 downto 0 ); irq_n_i : in std_logic; nmi_i : in std_logic; q_a_i : in std_logic_vector ( 7 downto 0 ); q_x_i : in std_logic_vector ( 7 downto 0 ); q_y_i : in std_logic_vector ( 7 downto 0 ); rdy_i : in std_logic; reg_0flag_i : in std_logic; reg_1flag_i : in std_logic; reg_7flag_i : in std_logic; rst_rst_n_i : in std_logic; so_n_i : in std_logic; a_o : out std_logic_vector (15 downto 0); adr_o : out std_logic_vector (15 downto 0); ch_a_o : out std_logic_vector ( 7 downto 0 ); ch_b_o : out std_logic_vector ( 7 downto 0 ); d_o : out std_logic_vector ( 7 downto 0 ); d_regs_in_o : out std_logic_vector ( 7 downto 0 ); ld_o : out std_logic_vector ( 1 downto 0 ); ld_pc_o : out std_logic; ld_sp_o : out std_logic; load_regs_o : out std_logic; offset_o : out std_logic_vector ( 15 downto 0 ); rd_o : out std_logic; rst_nmi_o : out std_logic; sel_pc_in_o : out std_logic; sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); sel_reg_o : out std_logic_vector ( 1 downto 0 ); sel_sp_as_o : out std_logic; sel_sp_in_o : out std_logic; sync_o : out std_logic; wr_n_o : out std_logic; wr_o : out std_logic ); -- Declarations end fsm_execution_unit ; -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.1210 2021/01/08 22:20:00 jens -- - Bug Fix rdy_i='0' causes hang after res_res_n_i='0' -> '1' -- at state RES1/s545 and malfunction of: -- STA ABS,Y state s208 -> no write of data -- STA (IND,X) state s209 -> no write of data -- Revision 1.1202 2018/09/10 12:14:00 jens -- - RESET generates SYNC now, 1 dead cycle delayed -- Revision 1.1202 RC 2018/09/09 03:00:00 jens -- - ADC / SBC flags and A like R65C02 now -- Revision 1.1202 BETA 2018/09/05 19:35:00 jens -- - BBRx/BBSx internal cycles like real 65C02 now -- - Bug Fix ADC and SBC in decimal mode (all op codes - -- 1 cycle is missing -- - Bug Fix ADC and SBC in decimal mode (all op codes - -- "Overflow" flag was computed wrong) -- Revision 1.1202 BETA 2018/09/02 18:49:00 jens -- - Interrupt NMI and IRQ processing via FETCH stage now -- Revision 1.1202 BETA 2018/08/30 15:39:00 jens -- - Interrupt priority order is now: BRQ - NMI - IRQ -- - Performance improvements on-going (Mealy -> Moore) -- Revision 1.1202 BETA 2018/08/23 20:27:00 jens -- - Bug Fixes All Branch Instructions -- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) -- 3 cycles now if branch forward occur and the branch -- instruction lies on a xxFEh location. -- (BBR, BBS) 6 cycles now if branch forward occur and the -- branch instruction lies on a xxFDh location. -- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now -- - Bug Fix Now all cycles are delayable (WR and internal) -- -- Revision 1.1201 BETA 2014/04/19 14:44:00 jens -- (never submitted to opencores) -- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. -- When the ABS address data bytes cross the page -- boundary (e.g. $02FE JMP hhll reads hh from -- $02FF and ll from $0200, instead $02FF and $0300) -- -- Revision 1.12 RC 2013/07/31 11:53:00 jens -- - Bug Fix CMP (IND) - wrongly decoded as function AND -- - Bug Fix BRK should clear decimal flag P Reg -- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address -- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created -- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) -- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed -- - Bug Fix RTI - should increment stack pointer (decremented) -- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. -- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong) -- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. -- -- Revision 1.11 2013/07/21 11:11:00 jens -- - Changing the title block and internal revision history -- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) -- -- Revision 1.10 2010/02/08 17:34:20 eda -- BUGFIX for IRQn, NMIn and RTI -- After detection of NMI or IRQ the address of the next instruction stacked wrong. -- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the -- vector address is not loaded yet. -- -- -- Revision 1.9 2010/02/08 17:32:19 eda -- BUGFIX for IRQn, NMIn and RTI -- After detection of NMI or IRQ the address of the next instruction stacked wrong. -- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the -- vector address is not loaded yet. -- -- -- Revision 1.8 2009/01/04 20:23:42 eda -- *** EMERGENCY BUGFIX *** -- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. -- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist -- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from -- $02FF and $0200, instead of $02FF and $0300) -- -- Revision 1.7 2009/01/04 16:54:59 eda -- - Removed unused bits in ALU (zw_ALUx) -- -- Revision 1.6 2009/01/04 10:27:49 eda -- Changes for cosmetic issues only -- -- Revision 1.5 2009/01/04 10:25:04 eda -- Changes for cosmetic issues only -- -- Revision 1.4 2009/01/03 16:53:01 eda -- - Unused nets and blocks deleted -- - Re-arragend symbols in block FSM_Execution_Unit -- - Renamed blocks -- - Input SO implemented -- -- Revision 1.3 2009/01/03 16:42:02 eda -- - Unused nets and blocks deleted -- - Re-arragend symbols in block FSM_Execution_Unit -- - Renamed blocks -- - Input SO implemented -- -- Revision 1.2 2008/12/31 19:31:24 eda -- Production Release -- -- -- -- r65c02_tc.fsm_execution_unit.fsm -- -- Date: 09.01.2021 -- Time: 17:10:06 -- By: VIVARE GmbH, Switzerland -- -- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; architecture fsm of fsm_execution_unit is -- Architecture Declarations signal reg_F : std_logic_vector( 7 DOWNTO 0 ); signal reg_PC : std_logic_vector(15 DOWNTO 0); signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); signal reg_sel_pc_in : std_logic; signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_sp_as : std_logic; signal reg_sel_sp_in : std_logic; signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); signal sig_PC : std_logic_vector(15 DOWNTO 0); signal sig_RD : std_logic; signal sig_RWn : std_logic; signal sig_SYNC : std_logic; signal sig_WR : std_logic; signal zw_100_a : std_logic; signal zw_100_alu : std_logic; signal zw_100_d : std_logic; signal zw_50_a : std_logic; signal zw_50_alu : std_logic; signal zw_50_d : std_logic; signal zw_ALU : std_logic_vector(9 DOWNTO 0); signal zw_ALU1 : std_logic_vector(9 DOWNTO 0); signal zw_ALU2 : std_logic_vector(9 DOWNTO 0); signal zw_ALU3 : std_logic_vector(9 DOWNTO 0); signal zw_ALU4 : std_logic_vector(9 DOWNTO 0); signal zw_ALU5 : std_logic_vector(9 DOWNTO 0); signal zw_ALU6 : std_logic_vector(9 DOWNTO 0); signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); signal zw_so : std_logic; signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); subtype state_type is std_logic_vector(7 downto 0); -- State vector declaration attribute state_vector : string; attribute state_vector of fsm : architecture is "current_state"; -- Hard encoding constant s544 : state_type := "00000000"; constant s545 : state_type := "00000001"; constant s546 : state_type := "00000011"; constant s547 : state_type := "00000010"; constant s549 : state_type := "00000110"; constant s550 : state_type := "00000111"; constant RES : state_type := "00000101"; constant FETCH : state_type := "00000100"; constant s6 : state_type := "00001100"; constant s7 : state_type := "00001101"; constant s8 : state_type := "00001111"; constant s9 : state_type := "00001110"; constant s10 : state_type := "00001010"; constant s13 : state_type := "00001011"; constant s18 : state_type := "00001001"; constant s19 : state_type := "00001000"; constant s26 : state_type := "00011000"; constant s27 : state_type := "00011001"; constant s203 : state_type := "00011011"; constant s204 : state_type := "00011010"; constant s212 : state_type := "00011110"; constant s216 : state_type := "00011111"; constant s219 : state_type := "00011101"; constant s220 : state_type := "00011100"; constant s227 : state_type := "00010100"; constant s228 : state_type := "00010101"; constant s230 : state_type := "00010111"; constant s231 : state_type := "00010110"; constant s229 : state_type := "00010010"; constant s512 : state_type := "00010011"; constant s554 : state_type := "00010001"; constant s578 : state_type := "00010000"; constant s581 : state_type := "00110000"; constant s582 : state_type := "00110001"; constant s583 : state_type := "00110011"; constant s584 : state_type := "00110010"; constant s585 : state_type := "00110110"; constant s586 : state_type := "00110111"; constant s587 : state_type := "00110101"; constant s580 : state_type := "00110100"; constant s178 : state_type := "00111100"; constant s194 : state_type := "00111101"; constant s195 : state_type := "00111111"; constant s196 : state_type := "00111110"; constant s197 : state_type := "00111010"; constant s198 : state_type := "00111011"; constant s199 : state_type := "00111001"; constant s200 : state_type := "00111000"; constant s205 : state_type := "00101000"; constant s206 : state_type := "00101001"; constant s207 : state_type := "00101011"; constant s208 : state_type := "00101010"; constant s209 : state_type := "00101110"; constant s213 : state_type := "00101111"; constant s214 : state_type := "00101101"; constant s513 : state_type := "00101100"; constant s588 : state_type := "00100100"; constant s589 : state_type := "00100101"; constant s590 : state_type := "00100111"; constant s591 : state_type := "00100110"; constant s592 : state_type := "00100010"; constant s593 : state_type := "00100011"; constant s594 : state_type := "00100001"; constant s595 : state_type := "00100000"; constant s596 : state_type := "01100000"; constant s597 : state_type := "01100001"; constant s405 : state_type := "01100011"; constant s408 : state_type := "01100010"; constant s410 : state_type := "01100110"; constant s411 : state_type := "01100111"; constant s414 : state_type := "01100101"; constant s415 : state_type := "01100100"; constant s417 : state_type := "01101100"; constant s419 : state_type := "01101101"; constant s420 : state_type := "01101111"; constant s598 : state_type := "01101110"; constant s599 : state_type := "01101010"; constant s600 : state_type := "01101011"; constant s268 : state_type := "01101001"; constant s305 : state_type := "01101000"; constant s306 : state_type := "01111000"; constant jmp1 : state_type := "01111001"; constant jmp2_1 : state_type := "01111011"; constant jmp4_12 : state_type := "01111010"; constant jmp_ex : state_type := "01111110"; constant jmp2_2 : state_type := "01111111"; constant jmp3_1 : state_type := "01111101"; constant s402 : state_type := "01111100"; constant s421 : state_type := "01110100"; constant s422 : state_type := "01110101"; constant s423 : state_type := "01110111"; constant s424 : state_type := "01110110"; constant s362 : state_type := "01110010"; constant s221 : state_type := "01110011"; constant s232 : state_type := "01110001"; constant s233 : state_type := "01110000"; constant s234 : state_type := "01010000"; constant s235 : state_type := "01010001"; constant brk1 : state_type := "01010011"; constant brk2 : state_type := "01010010"; constant brk3 : state_type := "01010110"; constant brk4 : state_type := "01010111"; constant brk6 : state_type := "01010101"; constant brk5 : state_type := "01010100"; constant s425 : state_type := "01011100"; constant s426 : state_type := "01011101"; constant s427 : state_type := "01011111"; constant s428 : state_type := "01011110"; constant s429 : state_type := "01011010"; constant s430 : state_type := "01011011"; constant s431 : state_type := "01011001"; constant s432 : state_type := "01011000"; constant s433 : state_type := "01001000"; constant s434 : state_type := "01001001"; constant s236 : state_type := "01001011"; constant s245 : state_type := "01001010"; constant s246 : state_type := "01001110"; constant s248 : state_type := "01001111"; constant s345 : state_type := "01001101"; constant s346 : state_type := "01001100"; constant s252 : state_type := "01000100"; constant s253 : state_type := "01000101"; constant s435 : state_type := "01000111"; constant s436 : state_type := "01000110"; constant s437 : state_type := "01000010"; constant s438 : state_type := "01000011"; constant s439 : state_type := "01000001"; constant s440 : state_type := "01000000"; constant s441 : state_type := "11000000"; constant s442 : state_type := "11000001"; constant s443 : state_type := "11000011"; constant s444 : state_type := "11000010"; constant irq1 : state_type := "11000110"; constant irq2 : state_type := "11000111"; constant irq3 : state_type := "11000101"; constant irq5b : state_type := "11000100"; constant irq5a : state_type := "11001100"; constant irq4 : state_type := "11001101"; constant irq6 : state_type := "11001111"; constant s11 : state_type := "11001110"; constant s12 : state_type := "11001010"; constant s20 : state_type := "11001011"; constant s14 : state_type := "11001001"; constant s21 : state_type := "11001000"; constant s23 : state_type := "11011000"; constant s15 : state_type := "11011001"; constant s25 : state_type := "11011011"; constant s28 : state_type := "11011010"; constant s16 : state_type := "11011110"; constant s30 : state_type := "11011111"; constant s31 : state_type := "11011101"; constant s32 : state_type := "11011100"; constant s33 : state_type := "11010100"; constant s34 : state_type := "11010101"; constant s36 : state_type := "11010111"; constant jmp3_2 : state_type := "11010110"; constant s601 : state_type := "11010010"; constant s602 : state_type := "11010011"; constant s270 : state_type := "11010001"; constant s307 : state_type := "11010000"; constant s308 : state_type := "11110000"; constant s271 : state_type := "11110001"; constant s272 : state_type := "11110011"; constant s309 : state_type := "11110010"; constant RES7 : state_type := "11110110"; -- Declare current and next state signals signal current_state : state_type; signal next_state : state_type; -- Declare any pre-registered internal signals signal d_o_cld : std_logic_vector ( 7 downto 0 ); signal rd_o_cld : std_logic ; signal sync_o_cld : std_logic ; signal wr_n_o_cld : std_logic ; signal wr_o_cld : std_logic ; begin ----------------------------------------------------------------- clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then current_state <= RES; -- Default Reset Values d_o_cld <= X"00"; rd_o_cld <= '1'; sync_o_cld <= '0'; wr_n_o_cld <= '1'; wr_o_cld <= '0'; reg_F <= "00110100"; reg_PC <= X"0000"; reg_PC1 <= X"0000"; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_rb_in <= "00"; reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_sp_as <= '0'; reg_sel_sp_in <= '0'; sig_PC <= X"0000"; zw_PC <= X"0000"; zw_REG_ALU <= '0' & X"00"; zw_REG_OP <= X"00"; zw_REG_sig_PC <= X"0000"; zw_b1 <= X"00"; zw_b2 <= X"00"; zw_b3 <= X"00"; zw_b4 <= X"00"; zw_so <= '0'; zw_w1 <= X"0000"; zw_w2 <= X"0000"; zw_w3 <= X"0000"; elsif (clk_clk_i'event and clk_clk_i = '1') then current_state <= next_state; -- Default Assignment To Internals reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); reg_PC <= reg_PC; reg_PC1 <= reg_PC1; reg_sel_pc_in <= reg_sel_pc_in; reg_sel_pc_val <= reg_sel_pc_val; reg_sel_rb_in <= reg_sel_rb_in; reg_sel_rb_out <= reg_sel_rb_out; reg_sel_reg <= reg_sel_reg; reg_sel_sp_as <= reg_sel_sp_as; reg_sel_sp_in <= reg_sel_sp_in; sig_PC <= sig_PC; zw_PC <= zw_PC; zw_REG_ALU <= zw_REG_ALU; zw_REG_OP <= zw_REG_OP; zw_REG_sig_PC <= zw_REG_sig_PC; zw_b1 <= zw_b1; zw_b2 <= zw_b2; zw_b3 <= zw_b3; zw_b4 <= zw_b4; zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); zw_w1 <= zw_w1; zw_w2 <= zw_w2; zw_w3 <= zw_w3; d_o_cld <= sig_D_OUT; rd_o_cld <= sig_RD; sync_o_cld <= sig_SYNC; wr_n_o_cld <= sig_RWn; wr_o_cld <= sig_WR; -- Combined Actions case current_state is when s544 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s545 => if (rdy_i = '1') then sig_PC <= adr_sp_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; end if; when s546 => if (rdy_i = '1') then sig_PC <= adr_pc_i; end if; when s547 => zw_w1 (7 downto 0) <= d_i; if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when s549 => reg_F(2) <= '1'; reg_F(3) <= '0'; reg_F(5) <= '1'; if (rdy_i = '1') then sig_PC <= d_i & zw_w1 (7 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s550 => if (rdy_i = '1') then sig_PC <= adr_sp_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "00"; end if; when RES => reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; when FETCH => zw_REG_OP <= d_i; if ((d_i = X"00") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((nmi_i = '1') and (rdy_i = '1')) then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; sig_PC <= adr_nxt_pc_i; zw_w3 <= adr_pc_i; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; sig_PC <= adr_nxt_pc_i; zw_w3 <= adr_pc_i; elsif ((d_i = X"58") and (rdy_i = '1')) then elsif ((d_i = X"28") and (rdy_i = '1')) then reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"78") and (rdy_i = '1')) then elsif ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71" or d_i = X"72") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E" or d_i (3 downto 0) = X"7" or d_i = X"14" or d_i = X"04" or d_i = X"0C" or d_i = X"1C") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70" or d_i = X"80") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"24" or d_i = X"2C" or d_i = X"3C" or d_i = X"34" or d_i = X"89") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"18") and (rdy_i = '1')) then elsif ((d_i = X"D8") and (rdy_i = '1')) then elsif ((d_i = X"8F" or d_i = X"9F" or d_i = X"AF" or d_i = X"BF" or d_i = X"CF" or d_i = X"DF" or d_i = X"EF" or d_i = X"FF" or d_i = X"0F" or d_i = X"1F" or d_i = X"2F" or d_i = X"3F" or d_i = X"4F" or d_i = X"5F" or d_i = X"6F" or d_i = X"7F") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"B8") and (rdy_i = '1')) then elsif ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") and (rdy_i = '1')) then zw_b4 <= X"FF"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"CA") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; elsif ((d_i = X"88") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; elsif ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1" or d_i = X"32" or d_i = X"D2" or d_i = X"52" or d_i = X"12") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") and (rdy_i = '1')) then zw_b4 <= X"01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"E8") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; elsif ((d_i = X"C8") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; elsif ((d_i = X"4C" or d_i = X"6C" or d_i = X"7C") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"20") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1" or d_i = X"B2") and (rdy_i = '1')) then reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") and (rdy_i = '1')) then reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") and (rdy_i = '1')) then reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"EA") and (rdy_i = '1')) then elsif ((d_i = X"48") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"08") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"7A") and (rdy_i = '1')) then reg_sel_reg <= "10"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"40") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"60") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1" or d_i = X"F2") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"38") and (rdy_i = '1')) then elsif ((d_i = X"F8") and (rdy_i = '1')) then elsif ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91" or d_i = X"92") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"86" or d_i = X"96" or d_i = X"8E") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"84" or d_i = X"94" or d_i = X"8C") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"AA") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "01"; reg_sel_rb_in <= "00"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"0A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"4A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"2A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"6A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; elsif ((d_i = X"A8") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "10"; reg_sel_rb_in <= "00"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"98") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; reg_sel_reg <= "00"; reg_sel_rb_in <= "01"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"BA") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"8A") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "00"; reg_sel_rb_in <= "10"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"9A") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; reg_sel_reg <= "11"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '1'; reg_sel_sp_as <= '0'; elsif ((d_i = X"DA") and (rdy_i = '1')) then reg_sel_rb_out <= "01"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"5A") and (rdy_i = '1')) then reg_sel_rb_out <= "10"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"68") and (rdy_i = '1')) then reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"FA") and (rdy_i = '1')) then reg_sel_reg <= "01"; reg_sel_rb_in <= "11"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '0'; elsif ((d_i = X"9C" or d_i = X"9E" or d_i = X"64" or d_i = X"74") and (rdy_i = '1')) then reg_sel_rb_out <= "11"; sig_PC <= adr_nxt_pc_i; elsif ((d_i = X"3A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; zw_b4 <= X"FF"; elsif ((d_i = X"1A") and (rdy_i = '1')) then reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; reg_sel_rb_in <= "11"; zw_b4 <= X"01"; elsif ((d_i = X"EA") and (rdy_i = '1')) then elsif ((d_i = X"02" or d_i = X"22" or d_i = X"42" or d_i = X"62" or d_i = X"82" or d_i = X"C2" or d_i = X"E2") and (rdy_i = '1')) then elsif ((d_i = X"44") and (rdy_i = '1')) then elsif ((d_i = X"54" or d_i = X"D4" or d_i = X"F4") and (rdy_i = '1')) then elsif ((d_i = X"DC" or d_i = X"FC") and (rdy_i = '1')) then elsif ((d_i = X"5C") and (rdy_i = '1')) then elsif ((d_i(3 downto 0) = X"3" or d_i(3 downto 0) = X"B") and (rdy_i = '1')) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s6 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s7 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s8 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(3) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s9 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(2) <= '1'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s10 => if (rdy_i = '1' and zw_REG_OP = X"9A") then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"BA") then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s13 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s18 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(3) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s19 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(2) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s26 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(6) <= '0'; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s27 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s203 => if (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then sig_PC <= X"00" & d_i; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then sig_PC <= adr_nxt_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"B6") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"32" OR zw_REG_OP = X"D2" OR zw_REG_OP = X"52" OR zw_REG_OP = X"B2" OR zw_REG_OP = X"12")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; end if; when s204 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s212 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s216 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s219 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s220 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s227 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s228 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s230 => if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s231 => if ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(0) <= zw_ALU(8); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s229 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_i; end if; when s512 => if (rdy_i = '1' and zw_REG_OP = X"65") then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"75") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"6D") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"7D") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"79") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"71") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"61") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR zw_ALU(0)); reg_F(0) <= zw_ALU4(4); elsif (rdy_i = '1' and zw_REG_OP = X"72") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; end if; when s554 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s578 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s581 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s582 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s583 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s584 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s585 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR zw_ALU(0)); reg_F(0) <= zw_ALU4(4); elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s586 => if (rdy_i = '1' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (NOT zw_ALU(7) AND (q_a_i(7)) AND (d_i(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR d_i(7))); reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR zw_ALU(0)); reg_F(0) <= zw_ALU4(4); end if; when s587 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s580 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_i; end if; when s178 => if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"64" OR zw_REG_OP = X"84")) then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"74" OR zw_REG_OP = X"94")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"9C" OR zw_REG_OP = X"8C")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"9D" OR zw_REG_OP = X"9E")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"99") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"91") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"81") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"96") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"92") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; end if; when s194 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s195 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s196 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s197 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s198 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s199 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s200 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s205 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s206 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s207 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s208 => if (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s209 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s213 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s214 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_i; end if; when s513 => if (rdy_i = '1' and zw_REG_OP = X"E5") then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR (zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"F5") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"ED") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"FD") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"F9") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"F1") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"E1") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') then sig_PC <= adr_nxt_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7)); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU2(4)); elsif (rdy_i = '1' and zw_REG_OP = X"F2") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; end if; when s588 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s589 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s590 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s591 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s592 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s593 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s594 => if (rdy_i = '1') then sig_PC <= X"00" & d_alu_i; zw_b1 <= d_i; end if; when s595 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR (zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7)); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU2(4)); elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s596 => if (rdy_i = '1' and reg_F(3) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (d_i(7))) OR (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT d_i(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT d_i(7))) OR (zw_ALU(8) AND (q_a_i(7)) AND (d_i(7))) OR (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))) OR (zw_ALU(8) AND (q_a_i(7)) AND (NOT d_i(7))); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1' and reg_F(3) = '1') then sig_PC <= adr_pc_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR d_i(7)); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU2(4)); end if; when s597 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; zw_b1 <= d_i; end if; when s405 => if (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46" or zw_REG_OP = X"04" or zw_REG_OP = X"14")) then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E"or zw_REG_OP = X"0C" or zw_REG_OP = X"1C")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP (3 downto 0) = X"7") then sig_PC <= X"00" & d_i; end if; when s408 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s410 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s411 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s414 => if (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s417 => if ((rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) and (rdy_i = '1')) then zw_b1 <= d_i(6 downto 0) & '0'; zw_b2(0) <= d_i(7); elsif ((rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) and (rdy_i = '1')) then zw_b1 <= '0' & d_i(7 downto 1); zw_b2(0) <= d_i(0); elsif ((rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) and (rdy_i = '1')) then zw_b1 <= d_i(6 downto 0) & reg_F(0); zw_b2(0) <= d_i(7); elsif ((rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) and (rdy_i = '1')) then zw_b1 <= reg_F(0) & d_i(7 downto 1); zw_b2(0) <= d_i(0); elsif ((rdy_i = '1' and zw_REG_OP (7) = '0' and zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then elsif ((rdy_i = '1' and zw_REG_OP (7) = '1' and zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then elsif ((rdy_i = '1' and (zw_REG_OP = X"14" or zw_REG_OP = X"1C")) and (rdy_i = '1')) then zw_b1 <= d_i and q_a_i; elsif ((rdy_i = '1' and (zw_REG_OP = X"04" or zw_REG_OP = X"0C")) and (rdy_i = '1')) then zw_b1 <= d_i and q_a_i; end if; when s419 => if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (((zw_REG_OP = X"14" or zw_REG_OP = X"04" or zw_REG_OP = X"0C" or zw_REG_OP = X"1C")) and (rdy_i = '1')) then reg_F(1) <= reg_1flag_i; sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then reg_F(0) <= zw_b2(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s420 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(7); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s598 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s599 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(0); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s600 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(0) <= q_a_i(7); reg_F(0) <= q_a_i(7); reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s268 => zw_b1 <= d_i; zw_b3 <= adr_nxt_pc_i (15 downto 8); zw_b2 <= d_i; if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "10"; end if; when s305 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); end if; when s306 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when jmp1 => zw_b1 <= d_i; if (rdy_i = '1' and zw_REG_OP = X"4C") then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"6C") then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "00"; elsif (rdy_i = '1' and zw_REG_OP = X"7C") then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "10"; end if; when jmp2_1 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; end if; when jmp4_12 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when jmp_ex => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when jmp2_2 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; end if; when s402 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s422 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s423 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when s424 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1 (7 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s362 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s221 => if (rdy_i = '1' and zw_REG_OP = X"34") then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and zw_REG_OP = X"3C") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; elsif (rdy_i = '1' and zw_REG_OP = X"24") then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and zw_REG_OP = X"2C") then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and zw_REG_OP = X"89") then sig_PC <= adr_nxt_pc_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s232 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s233 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s234 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= d_i(7); reg_F(6) <= d_i(6); reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s235 => if (rdy_i = '1' AND zw_b2(0) = '0') then sig_PC <= adr_pc_i; reg_F(7) <= d_i(7); reg_F(6) <= d_i(6); reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when brk1 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when brk2 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when brk3 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when brk4 => if (rdy_i = '1') then sig_PC <= X"FFFE"; end if; when brk6 => reg_F(2) <= '1'; reg_F(3) <= '0'; if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when brk5 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= X"FFFF"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when s425 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s426 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s427 => reg_F(7 downto 6) <= d_i(7 downto 6); reg_F(3 downto 0) <= d_i(3 downto 0); if (rdy_i = '1') then sig_PC <= adr_sp_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when s428 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s429 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s430 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s431 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s432 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= adr_sp_i; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "00"; end if; when s433 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s434 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s236 => if (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) then sig_PC <= X"00" & d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) then sig_PC <= X"00" & d_i; zw_b1 <= d_alu_i; elsif (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_i; elsif (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) then sig_PC <= adr_nxt_pc_i; zw_b1 <= d_alu_i; zw_b2(0) <= reg_0flag_i; end if; when s245 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; end if; when s246 => if (rdy_i = '1') then sig_PC <= d_i & zw_b1; zw_b3 <= d_alu_i; end if; when s248 => if (rdy_i = '1') then sig_PC <= X"00" & zw_b1; end if; when s345 => if (rdy_i = '1') then sig_PC <= zw_b3 & zw_b1; end if; when s346 => if (rdy_i = '1') then zw_b1 <= d_alu_i; end if; when s253 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s435 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s436 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s437 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s438 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s440 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s441 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7) <= reg_7flag_i; reg_F(1) <= reg_1flag_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s443 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when s444 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_F(7 downto 6) <= d_i(7 downto 6); reg_F(3 downto 0) <= d_i(3 downto 0); reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when irq1 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when irq2 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when irq3 => if (rdy_i = '1') then sig_PC <= adr_sp_i; end if; when irq5b => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= X"FFFF"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when irq5a => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= X"FFFB"; reg_sel_pc_in <= '1'; reg_sel_pc_val <= "11"; end if; when irq4 => if (rdy_i = '1' and nmi_i = '1') then sig_PC <= X"FFFA"; elsif (rdy_i = '1') then sig_PC <= X"FFFE"; end if; when irq6 => reg_F(2) <= '1'; reg_F(3) <= '0'; if (rdy_i = '1') then sig_PC <= d_i & zw_b1; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s11 => if (rdy_i = '1') then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s20 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s23 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s28 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s33 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when jmp3_2 => if (rdy_i = '1') then sig_PC <= adr_pc_i; end if; when s601 => if (rdy_i = '1') then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s602 => if (rdy_i = '1') then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when s270 => if (rdy_i = '1') then sig_PC <= X"00" & d_i; end if; when s307 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); end if; when s308 => zw_b2 <= d_i; zw_b3 <= adr_nxt_pc_i (15 downto 8); if (rdy_i = '1' and ( (zw_b1(0) = '0' and zw_REG_OP = X"8F") or (zw_b1(1) = '0' and zw_REG_OP = X"9F") or (zw_b1(2) = '0' and zw_REG_OP = X"AF") or (zw_b1(3) = '0' and zw_REG_OP = X"BF") or (zw_b1(4) = '0' and zw_REG_OP = X"CF") or (zw_b1(5) = '0' and zw_REG_OP = X"DF") or (zw_b1(6) = '0' and zw_REG_OP = X"EF") or (zw_b1(7) = '0' and zw_REG_OP = X"FF") or (zw_b1(0) = '1' and zw_REG_OP = X"0F") or (zw_b1(1) = '1' and zw_REG_OP = X"1F") or (zw_b1(2) = '1' and zw_REG_OP = X"2F") or (zw_b1(3) = '1' and zw_REG_OP = X"3F") or (zw_b1(4) = '1' and zw_REG_OP = X"4F") or (zw_b1(5) = '1' and zw_REG_OP = X"5F") or (zw_b1(6) = '1' and zw_REG_OP = X"6F") or (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; elsif (rdy_i = '1') then reg_sel_pc_in <= '0'; reg_sel_pc_val <= "10"; end if; when s272 => zw_b1 <= d_i; if (rdy_i = '1') then sig_PC <= adr_pc_i; end if; when s309 => if (rdy_i = '1') then sig_PC <= adr_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; end if; when RES7 => sig_PC <= adr_nxt_pc_i; reg_sel_pc_in <= '0'; reg_sel_pc_val <= "00"; reg_sel_sp_in <= '0'; reg_sel_sp_as <= '1'; when others => null; end case; end if; end process clocked_proc; ----------------------------------------------------------------- nextstate_proc : process ( adr_nxt_pc_i, current_state, d_i, irq_n_i, nmi_i, rdy_i, reg_F, zw_REG_OP, zw_b1, zw_b2, zw_b3 ) ----------------------------------------------------------------- begin case current_state is when s544 => if (rdy_i = '1') then next_state <= s550; else next_state <= s544; end if; when s545 => if (rdy_i = '1') then next_state <= s546; else next_state <= s545; end if; when s546 => if (rdy_i = '1') then next_state <= s547; else next_state <= s546; end if; when s547 => if (rdy_i = '1') then next_state <= s549; else next_state <= s547; end if; when s549 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s549; end if; when s550 => if (rdy_i = '1') then next_state <= s545; else next_state <= s550; end if; when RES => next_state <= RES7; when FETCH => if ((d_i = X"00") and (rdy_i = '1')) then next_state <= brk1; elsif ((nmi_i = '1') and (rdy_i = '1')) then next_state <= irq1; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then next_state <= irq1; elsif ((d_i = X"58") and (rdy_i = '1')) then next_state <= s19; elsif ((d_i = X"28") and (rdy_i = '1')) then next_state <= s442; elsif ((d_i = X"78") and (rdy_i = '1')) then next_state <= s9; elsif ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71" or d_i = X"72") and (rdy_i = '1')) then next_state <= s512; elsif ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E" or d_i (3 downto 0) = X"7" or d_i = X"14" or d_i = X"04" or d_i = X"0C" or d_i = X"1C") and (rdy_i = '1')) then next_state <= s405; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70" or d_i = X"80") and (rdy_i = '1')) then next_state <= s268; elsif ((d_i = X"24" or d_i = X"2C" or d_i = X"3C" or d_i = X"34" or d_i = X"89") and (rdy_i = '1')) then next_state <= s221; elsif ((d_i = X"18") and (rdy_i = '1')) then next_state <= s13; elsif ((d_i = X"D8") and (rdy_i = '1')) then next_state <= s18; elsif ((d_i = X"8F" or d_i = X"9F" or d_i = X"AF" or d_i = X"BF" or d_i = X"CF" or d_i = X"DF" or d_i = X"EF" or d_i = X"FF" or d_i = X"0F" or d_i = X"1F" or d_i = X"2F" or d_i = X"3F" or d_i = X"4F" or d_i = X"5F" or d_i = X"6F" or d_i = X"7F") and (rdy_i = '1')) then next_state <= s270; elsif ((d_i = X"B8") and (rdy_i = '1')) then next_state <= s26; elsif ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") and (rdy_i = '1')) then next_state <= s203; elsif ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") and (rdy_i = '1')) then next_state <= s203; elsif ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") and (rdy_i = '1')) then next_state <= s236; elsif ((d_i = X"CA") and (rdy_i = '1')) then next_state <= s27; elsif ((d_i = X"88") and (rdy_i = '1')) then next_state <= s27; elsif ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1" or d_i = X"32" or d_i = X"D2" or d_i = X"52" or d_i = X"12") and (rdy_i = '1')) then next_state <= s203; elsif ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") and (rdy_i = '1')) then next_state <= s236; elsif ((d_i = X"E8") and (rdy_i = '1')) then next_state <= s27; elsif ((d_i = X"C8") and (rdy_i = '1')) then next_state <= s27; elsif ((d_i = X"4C" or d_i = X"6C" or d_i = X"7C") and (rdy_i = '1')) then next_state <= jmp1; elsif ((d_i = X"20") and (rdy_i = '1')) then next_state <= s402; elsif ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1" or d_i = X"B2") and (rdy_i = '1')) then next_state <= s203; elsif ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") and (rdy_i = '1')) then next_state <= s203; elsif ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") and (rdy_i = '1')) then next_state <= s203; elsif ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") and (rdy_i = '1')) then next_state <= s405; elsif ((d_i = X"EA") and (rdy_i = '1')) then next_state <= s6; elsif ((d_i = X"48") and (rdy_i = '1')) then next_state <= s435; elsif ((d_i = X"08") and (rdy_i = '1')) then next_state <= s437; elsif ((d_i = X"7A") and (rdy_i = '1')) then next_state <= s439; elsif ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") and (rdy_i = '1')) then next_state <= s405; elsif ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") and (rdy_i = '1')) then next_state <= s405; elsif ((d_i = X"40") and (rdy_i = '1')) then next_state <= s425; elsif ((d_i = X"60") and (rdy_i = '1')) then next_state <= s430; elsif ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1" or d_i = X"F2") and (rdy_i = '1')) then next_state <= s513; elsif ((d_i = X"38") and (rdy_i = '1')) then next_state <= s7; elsif ((d_i = X"F8") and (rdy_i = '1')) then next_state <= s8; elsif ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91" or d_i = X"92") and (rdy_i = '1')) then next_state <= s178; elsif ((d_i = X"86" or d_i = X"96" or d_i = X"8E") and (rdy_i = '1')) then next_state <= s178; elsif ((d_i = X"84" or d_i = X"94" or d_i = X"8C") and (rdy_i = '1')) then next_state <= s178; elsif ((d_i = X"AA") and (rdy_i = '1')) then next_state <= s10; elsif ((d_i = X"0A") and (rdy_i = '1')) then next_state <= s420; elsif ((d_i = X"4A") and (rdy_i = '1')) then next_state <= s599; elsif ((d_i = X"2A") and (rdy_i = '1')) then next_state <= s600; elsif ((d_i = X"6A") and (rdy_i = '1')) then next_state <= s598; elsif ((d_i = X"A8") and (rdy_i = '1')) then next_state <= s10; elsif ((d_i = X"98") and (rdy_i = '1')) then next_state <= s10; elsif ((d_i = X"BA") and (rdy_i = '1')) then next_state <= s10; elsif ((d_i = X"8A") and (rdy_i = '1')) then next_state <= s10; elsif ((d_i = X"9A") and (rdy_i = '1')) then next_state <= s10; elsif ((d_i = X"DA") and (rdy_i = '1')) then next_state <= s435; elsif ((d_i = X"5A") and (rdy_i = '1')) then next_state <= s435; elsif ((d_i = X"68") and (rdy_i = '1')) then next_state <= s439; elsif ((d_i = X"FA") and (rdy_i = '1')) then next_state <= s439; elsif ((d_i = X"9C" or d_i = X"9E" or d_i = X"64" or d_i = X"74") and (rdy_i = '1')) then next_state <= s178; elsif ((d_i = X"3A") and (rdy_i = '1')) then next_state <= s27; elsif ((d_i = X"1A") and (rdy_i = '1')) then next_state <= s27; elsif ((d_i = X"EA") and (rdy_i = '1')) then next_state <= s6; elsif ((d_i = X"02" or d_i = X"22" or d_i = X"42" or d_i = X"62" or d_i = X"82" or d_i = X"C2" or d_i = X"E2") and (rdy_i = '1')) then next_state <= s11; elsif ((d_i = X"44") and (rdy_i = '1')) then next_state <= s12; elsif ((d_i = X"54" or d_i = X"D4" or d_i = X"F4") and (rdy_i = '1')) then next_state <= s14; elsif ((d_i = X"DC" or d_i = X"FC") and (rdy_i = '1')) then next_state <= s15; elsif ((d_i = X"5C") and (rdy_i = '1')) then next_state <= s16; elsif ((d_i(3 downto 0) = X"3" or d_i(3 downto 0) = X"B") and (rdy_i = '1')) then next_state <= FETCH; else next_state <= FETCH; end if; when s6 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s6; end if; when s7 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s7; end if; when s8 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s8; end if; when s9 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s9; end if; when s10 => if (rdy_i = '1' and zw_REG_OP = X"9A") then next_state <= FETCH; elsif (rdy_i = '1' and zw_REG_OP = X"BA") then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= FETCH; else next_state <= s10; end if; when s13 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s13; end if; when s18 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s18; end if; when s19 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s19; end if; when s26 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s26; end if; when s27 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s27; end if; when s203 => if (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then next_state <= s230; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then next_state <= FETCH; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then next_state <= FETCH; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then next_state <= FETCH; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then next_state <= FETCH; elsif (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then next_state <= FETCH; elsif (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) then next_state <= s219; elsif (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) then next_state <= s204; elsif (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) then next_state <= s212; elsif (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) then next_state <= s212; elsif (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) then next_state <= s216; elsif (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) then next_state <= s220; elsif (rdy_i = '1' and zw_REG_OP = X"B6") then next_state <= s219; elsif (rdy_i = '1' and (zw_REG_OP = X"32" OR zw_REG_OP = X"D2" OR zw_REG_OP = X"52" OR zw_REG_OP = X"B2" OR zw_REG_OP = X"12")) then next_state <= s229; else next_state <= s203; end if; when s204 => if (rdy_i = '1') then next_state <= s230; else next_state <= s204; end if; when s212 => if (rdy_i = '1') then next_state <= s231; else next_state <= s212; end if; when s216 => if (rdy_i = '1') then next_state <= s228; else next_state <= s216; end if; when s219 => if (rdy_i = '1') then next_state <= s230; else next_state <= s219; end if; when s220 => if (rdy_i = '1') then next_state <= s227; else next_state <= s220; end if; when s227 => if (rdy_i = '1') then next_state <= s204; else next_state <= s227; end if; when s228 => if (rdy_i = '1') then next_state <= s231; else next_state <= s228; end if; when s230 => if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then next_state <= FETCH; elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then next_state <= FETCH; elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then next_state <= FETCH; elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= FETCH; else next_state <= s230; end if; when s231 => if ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then next_state <= FETCH; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then next_state <= FETCH; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then next_state <= FETCH; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then next_state <= FETCH; elsif (rdy_i = '1' AND zw_b2(0) = '0') then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s230; else next_state <= s231; end if; when s229 => if (rdy_i = '1') then next_state <= s204; else next_state <= s229; end if; when s512 => if (rdy_i = '1' and zw_REG_OP = X"65") then next_state <= s586; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') then next_state <= FETCH; elsif (rdy_i = '1' and zw_REG_OP = X"75") then next_state <= s582; elsif (rdy_i = '1' and zw_REG_OP = X"6D") then next_state <= s554; elsif (rdy_i = '1' and zw_REG_OP = X"7D") then next_state <= s578; elsif (rdy_i = '1' and zw_REG_OP = X"79") then next_state <= s578; elsif (rdy_i = '1' and zw_REG_OP = X"71") then next_state <= s581; elsif (rdy_i = '1' and zw_REG_OP = X"61") then next_state <= s583; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') then next_state <= s601; elsif (rdy_i = '1' and zw_REG_OP = X"72") then next_state <= s580; else next_state <= s512; end if; when s554 => if (rdy_i = '1') then next_state <= s586; else next_state <= s554; end if; when s578 => if (rdy_i = '1') then next_state <= s585; else next_state <= s578; end if; when s581 => if (rdy_i = '1') then next_state <= s587; else next_state <= s581; end if; when s582 => if (rdy_i = '1') then next_state <= s586; else next_state <= s582; end if; when s583 => if (rdy_i = '1') then next_state <= s584; else next_state <= s583; end if; when s584 => if (rdy_i = '1') then next_state <= s554; else next_state <= s584; end if; when s585 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then next_state <= FETCH; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then next_state <= s601; elsif (rdy_i = '1') then next_state <= s586; else next_state <= s585; end if; when s586 => if (rdy_i = '1' and reg_F(3) = '0') then next_state <= FETCH; elsif (rdy_i = '1' and reg_F(3) = '1') then next_state <= s601; else next_state <= s586; end if; when s587 => if (rdy_i = '1') then next_state <= s585; else next_state <= s587; end if; when s580 => if (rdy_i = '1') then next_state <= s554; else next_state <= s580; end if; when s178 => if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"64" OR zw_REG_OP = X"84")) then next_state <= s197; elsif (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"74" OR zw_REG_OP = X"94")) then next_state <= s198; elsif (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"9C" OR zw_REG_OP = X"8C")) then next_state <= s196; elsif (rdy_i = '1' and (zw_REG_OP = X"9D" OR zw_REG_OP = X"9E")) then next_state <= s194; elsif (rdy_i = '1' and zw_REG_OP = X"99") then next_state <= s194; elsif (rdy_i = '1' and zw_REG_OP = X"91") then next_state <= s195; elsif (rdy_i = '1' and zw_REG_OP = X"81") then next_state <= s199; elsif (rdy_i = '1' and zw_REG_OP = X"96") then next_state <= s198; elsif (rdy_i = '1' and zw_REG_OP = X"92") then next_state <= s214; else next_state <= s178; end if; when s194 => if (rdy_i = '1') then next_state <= s208; else next_state <= s194; end if; when s195 => if (rdy_i = '1') then next_state <= s206; else next_state <= s195; end if; when s196 => if (rdy_i = '1') then next_state <= s200; else next_state <= s196; end if; when s197 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s197; end if; when s198 => if (rdy_i = '1') then next_state <= s207; else next_state <= s198; end if; when s199 => if (rdy_i = '1') then next_state <= s205; else next_state <= s199; end if; when s200 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s200; end if; when s205 => if (rdy_i = '1') then next_state <= s209; else next_state <= s205; end if; when s206 => if (rdy_i = '1') then next_state <= s208; else next_state <= s206; end if; when s207 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s207; end if; when s208 => if (rdy_i = '1') then next_state <= s213; else next_state <= s208; end if; when s209 => if (rdy_i = '1') then next_state <= s213; else next_state <= s209; end if; when s213 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s213; end if; when s214 => if (rdy_i = '1') then next_state <= s196; else next_state <= s214; end if; when s513 => if (rdy_i = '1' and zw_REG_OP = X"E5") then next_state <= s596; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') then next_state <= FETCH; elsif (rdy_i = '1' and zw_REG_OP = X"F5") then next_state <= s591; elsif (rdy_i = '1' and zw_REG_OP = X"ED") then next_state <= s588; elsif (rdy_i = '1' and zw_REG_OP = X"FD") then next_state <= s589; elsif (rdy_i = '1' and zw_REG_OP = X"F9") then next_state <= s589; elsif (rdy_i = '1' and zw_REG_OP = X"F1") then next_state <= s590; elsif (rdy_i = '1' and zw_REG_OP = X"E1") then next_state <= s592; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') then next_state <= s602; elsif (rdy_i = '1' and zw_REG_OP = X"F2") then next_state <= s597; else next_state <= s513; end if; when s588 => if (rdy_i = '1') then next_state <= s596; else next_state <= s588; end if; when s589 => if (rdy_i = '1') then next_state <= s595; else next_state <= s589; end if; when s590 => if (rdy_i = '1') then next_state <= s593; else next_state <= s590; end if; when s591 => if (rdy_i = '1') then next_state <= s596; else next_state <= s591; end if; when s592 => if (rdy_i = '1') then next_state <= s594; else next_state <= s592; end if; when s593 => if (rdy_i = '1') then next_state <= s595; else next_state <= s593; end if; when s594 => if (rdy_i = '1') then next_state <= s588; else next_state <= s594; end if; when s595 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then next_state <= FETCH; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then next_state <= s602; elsif (rdy_i = '1') then next_state <= s596; else next_state <= s595; end if; when s596 => if (rdy_i = '1' and reg_F(3) = '0') then next_state <= FETCH; elsif (rdy_i = '1' and reg_F(3) = '1') then next_state <= s602; else next_state <= s596; end if; when s597 => if (rdy_i = '1') then next_state <= s588; else next_state <= s597; end if; when s405 => if (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) then next_state <= s410; elsif (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46" or zw_REG_OP = X"04" or zw_REG_OP = X"14")) then next_state <= s415; elsif (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) then next_state <= s411; elsif (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E"or zw_REG_OP = X"0C" or zw_REG_OP = X"1C")) then next_state <= s408; elsif (rdy_i = '1' and zw_REG_OP (3 downto 0) = X"7") then next_state <= s415; else next_state <= s405; end if; when s408 => if (rdy_i = '1') then next_state <= s415; else next_state <= s408; end if; when s410 => if (rdy_i = '1') then next_state <= s414; else next_state <= s410; end if; when s411 => if (rdy_i = '1') then next_state <= s415; else next_state <= s411; end if; when s414 => if (rdy_i = '1') then next_state <= s417; else next_state <= s414; end if; when s415 => if (rdy_i = '1') then next_state <= s417; else next_state <= s415; end if; when s417 => if ((rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and zw_REG_OP (7) = '0' and zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and zw_REG_OP (7) = '1' and zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and (zw_REG_OP = X"14" or zw_REG_OP = X"1C")) and (rdy_i = '1')) then next_state <= s419; elsif ((rdy_i = '1' and (zw_REG_OP = X"04" or zw_REG_OP = X"0C")) and (rdy_i = '1')) then next_state <= s419; else next_state <= s417; end if; when s419 => if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then next_state <= FETCH; elsif (((zw_REG_OP = X"14" or zw_REG_OP = X"04" or zw_REG_OP = X"0C" or zw_REG_OP = X"1C")) and (rdy_i = '1')) then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= FETCH; else next_state <= s419; end if; when s420 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s420; end if; when s598 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s598; end if; when s599 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s599; end if; when s600 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s600; end if; when s268 => if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s305; else next_state <= s268; end if; when s305 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s306; else next_state <= s305; end if; when s306 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s306; end if; when jmp1 => if (rdy_i = '1' and zw_REG_OP = X"4C") then next_state <= jmp_ex; elsif (rdy_i = '1' and zw_REG_OP = X"6C") then next_state <= jmp2_1; elsif (rdy_i = '1' and zw_REG_OP = X"7C") then next_state <= jmp2_2; else next_state <= jmp1; end if; when jmp2_1 => if (rdy_i = '1') then next_state <= jmp3_1; else next_state <= jmp2_1; end if; when jmp4_12 => if (rdy_i = '1') then next_state <= jmp_ex; else next_state <= jmp4_12; end if; when jmp_ex => if (rdy_i = '1') then next_state <= FETCH; else next_state <= jmp_ex; end if; when jmp2_2 => if (rdy_i = '1') then next_state <= jmp3_2; else next_state <= jmp2_2; end if; when jmp3_1 => if (rdy_i = '1') then next_state <= jmp4_12; else next_state <= jmp3_1; end if; when s402 => if (rdy_i = '1') then next_state <= s421; else next_state <= s402; end if; when s421 => if (rdy_i = '1') then next_state <= s422; else next_state <= s421; end if; when s422 => if (rdy_i = '1') then next_state <= s423; else next_state <= s422; end if; when s423 => if (rdy_i = '1') then next_state <= s424; else next_state <= s423; end if; when s424 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s424; end if; when s362 => if (rdy_i = '1') then next_state <= s234; else next_state <= s362; end if; when s221 => if (rdy_i = '1' and zw_REG_OP = X"34") then next_state <= s233; elsif (rdy_i = '1' and zw_REG_OP = X"3C") then next_state <= s232; elsif (rdy_i = '1' and zw_REG_OP = X"24") then next_state <= s234; elsif (rdy_i = '1' and zw_REG_OP = X"2C") then next_state <= s362; elsif (rdy_i = '1' and zw_REG_OP = X"89") then next_state <= FETCH; else next_state <= s221; end if; when s232 => if (rdy_i = '1') then next_state <= s235; else next_state <= s232; end if; when s233 => if (rdy_i = '1') then next_state <= s234; else next_state <= s233; end if; when s234 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s234; end if; when s235 => if (rdy_i = '1' AND zw_b2(0) = '0') then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s234; else next_state <= s235; end if; when brk1 => if (rdy_i = '1') then next_state <= brk2; else next_state <= brk1; end if; when brk2 => if (rdy_i = '1') then next_state <= brk3; else next_state <= brk2; end if; when brk3 => if (rdy_i = '1') then next_state <= brk4; else next_state <= brk3; end if; when brk4 => if (rdy_i = '1') then next_state <= brk5; else next_state <= brk4; end if; when brk6 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= brk6; end if; when brk5 => if (rdy_i = '1') then next_state <= brk6; else next_state <= brk5; end if; when s425 => if (rdy_i = '1') then next_state <= s426; else next_state <= s425; end if; when s426 => if (rdy_i = '1') then next_state <= s427; else next_state <= s426; end if; when s427 => if (rdy_i = '1') then next_state <= s428; else next_state <= s427; end if; when s428 => if (rdy_i = '1') then next_state <= s429; else next_state <= s428; end if; when s429 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s429; end if; when s430 => if (rdy_i = '1') then next_state <= s431; else next_state <= s430; end if; when s431 => if (rdy_i = '1') then next_state <= s432; else next_state <= s431; end if; when s432 => if (rdy_i = '1') then next_state <= s433; else next_state <= s432; end if; when s433 => if (rdy_i = '1') then next_state <= s434; else next_state <= s433; end if; when s434 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s434; end if; when s236 => if (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) then next_state <= s346; elsif (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) then next_state <= s248; elsif (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) then next_state <= s245; elsif (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) then next_state <= s246; else next_state <= s236; end if; when s245 => if (rdy_i = '1') then next_state <= s346; else next_state <= s245; end if; when s246 => if (rdy_i = '1') then next_state <= s345; else next_state <= s246; end if; when s248 => if (rdy_i = '1') then next_state <= s346; else next_state <= s248; end if; when s345 => if (rdy_i = '1') then next_state <= s346; else next_state <= s345; end if; when s346 => if (rdy_i = '1') then next_state <= s252; else next_state <= s346; end if; when s252 => if (rdy_i = '1') then next_state <= s253; else next_state <= s252; end if; when s253 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s253; end if; when s435 => if (rdy_i = '1') then next_state <= s436; else next_state <= s435; end if; when s436 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s436; end if; when s437 => if (rdy_i = '1') then next_state <= s438; else next_state <= s437; end if; when s438 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s438; end if; when s439 => if (rdy_i = '1') then next_state <= s440; else next_state <= s439; end if; when s440 => if (rdy_i = '1') then next_state <= s441; else next_state <= s440; end if; when s441 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s441; end if; when s442 => if (rdy_i = '1') then next_state <= s443; else next_state <= s442; end if; when s443 => if (rdy_i = '1') then next_state <= s444; else next_state <= s443; end if; when s444 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s444; end if; when irq1 => if (rdy_i = '1') then next_state <= irq2; else next_state <= irq1; end if; when irq2 => if (rdy_i = '1') then next_state <= irq3; else next_state <= irq2; end if; when irq3 => if (rdy_i = '1') then next_state <= irq4; else next_state <= irq3; end if; when irq5b => if (rdy_i = '1') then next_state <= irq6; else next_state <= irq5b; end if; when irq5a => if (rdy_i = '1') then next_state <= irq6; else next_state <= irq5a; end if; when irq4 => if (rdy_i = '1' and nmi_i = '1') then next_state <= irq5a; elsif (rdy_i = '1') then next_state <= irq5b; else next_state <= irq4; end if; when irq6 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= irq6; end if; when s11 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s11; end if; when s12 => if (rdy_i = '1') then next_state <= s20; else next_state <= s12; end if; when s20 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s20; end if; when s14 => if (rdy_i = '1') then next_state <= s21; else next_state <= s14; end if; when s21 => if (rdy_i = '1') then next_state <= s23; else next_state <= s21; end if; when s23 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s23; end if; when s15 => if (rdy_i = '1') then next_state <= s25; else next_state <= s15; end if; when s25 => if (rdy_i = '1') then next_state <= s28; else next_state <= s25; end if; when s28 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s28; end if; when s16 => if (rdy_i = '1') then next_state <= s30; else next_state <= s16; end if; when s30 => if (rdy_i = '1') then next_state <= s31; else next_state <= s30; end if; when s31 => if (rdy_i = '1') then next_state <= s32; else next_state <= s31; end if; when s32 => if (rdy_i = '1') then next_state <= s34; else next_state <= s32; end if; when s33 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s33; end if; when s34 => if (rdy_i = '1') then next_state <= s36; else next_state <= s34; end if; when s36 => if (rdy_i = '1') then next_state <= s33; else next_state <= s36; end if; when jmp3_2 => if (rdy_i = '1') then next_state <= jmp4_12; else next_state <= jmp3_2; end if; when s601 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s601; end if; when s602 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s602; end if; when s270 => if (rdy_i = '1') then next_state <= s271; else next_state <= s270; end if; when s307 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s309; else next_state <= s307; end if; when s308 => if (rdy_i = '1' and ( (zw_b1(0) = '0' and zw_REG_OP = X"8F") or (zw_b1(1) = '0' and zw_REG_OP = X"9F") or (zw_b1(2) = '0' and zw_REG_OP = X"AF") or (zw_b1(3) = '0' and zw_REG_OP = X"BF") or (zw_b1(4) = '0' and zw_REG_OP = X"CF") or (zw_b1(5) = '0' and zw_REG_OP = X"DF") or (zw_b1(6) = '0' and zw_REG_OP = X"EF") or (zw_b1(7) = '0' and zw_REG_OP = X"FF") or (zw_b1(0) = '1' and zw_REG_OP = X"0F") or (zw_b1(1) = '1' and zw_REG_OP = X"1F") or (zw_b1(2) = '1' and zw_REG_OP = X"2F") or (zw_b1(3) = '1' and zw_REG_OP = X"3F") or (zw_b1(4) = '1' and zw_REG_OP = X"4F") or (zw_b1(5) = '1' and zw_REG_OP = X"5F") or (zw_b1(6) = '1' and zw_REG_OP = X"6F") or (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then next_state <= FETCH; elsif (rdy_i = '1') then next_state <= s307; else next_state <= s308; end if; when s271 => if (rdy_i = '1') then next_state <= s272; else next_state <= s271; end if; when s272 => if (rdy_i = '1') then next_state <= s308; else next_state <= s272; end if; when s309 => if (rdy_i = '1') then next_state <= FETCH; else next_state <= s309; end if; when RES7 => next_state <= s544; when others => next_state <= RES; end case; end process nextstate_proc; ----------------------------------------------------------------- output_proc : process ( adr_nxt_pc_i, adr_pc_i, adr_sp_i, current_state, d_alu_i, d_alu_prio_i, d_i, d_regs_out_i, irq_n_i, nmi_i, q_a_i, q_x_i, q_y_i, rdy_i, reg_F, reg_sel_pc_in, reg_sel_pc_val, reg_sel_rb_in, reg_sel_rb_out, reg_sel_reg, reg_sel_sp_as, reg_sel_sp_in, sig_PC, zw_ALU, zw_ALU1, zw_ALU2, zw_ALU3, zw_ALU4, zw_ALU5, zw_ALU6, zw_REG_OP, zw_b1, zw_b2, zw_b3, zw_b4, zw_w1, zw_w3 ) ----------------------------------------------------------------- begin -- Default Assignment a_o <= sig_PC; adr_o <= X"0000"; ch_a_o <= X"00"; ch_b_o <= X"00"; d_regs_in_o <= X"00"; ld_o <= "00"; ld_pc_o <= '0'; ld_sp_o <= '0'; load_regs_o <= '0'; offset_o <= X"0000"; rst_nmi_o <= '0'; sel_pc_in_o <= reg_sel_pc_in; sel_pc_val_o <= reg_sel_pc_val; sel_rb_in_o <= reg_sel_rb_in; sel_rb_out_o <= reg_sel_rb_out; sel_reg_o <= reg_sel_reg; sel_sp_as_o <= reg_sel_sp_as; sel_sp_in_o <= reg_sel_sp_in; -- Default Assignment To Internals sig_D_OUT <= X"00"; sig_RD <= '1'; sig_RWn <= '1'; sig_SYNC <= '0'; sig_WR <= '0'; zw_100_a <= '0'; zw_100_alu <= '0'; zw_100_d <= '0'; zw_50_a <= '0'; zw_50_alu <= '0'; zw_50_d <= '0'; zw_ALU <= "00" & X"00"; zw_ALU1 <= "00" & X"00"; zw_ALU2 <= "00" & X"00"; zw_ALU3 <= "00" & X"00"; zw_ALU4 <= "00" & X"00"; zw_ALU5 <= "00" & X"00"; zw_ALU6 <= "00" & X"00"; -- Combined Actions case current_state is when s544 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s545 => adr_o <= X"FFFB"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s546 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s549 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_w1 (7 downto 0); ld_o <= "11"; sig_SYNC <= '1'; end if; when s550 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when RES => sig_SYNC <= '1'; when FETCH => sig_RWn <= '1'; sig_RD <= '1'; sig_SYNC <= NOT (rdy_i); ld_pc_o <= '1'; if ((d_i = X"00") and (rdy_i = '1')) then ld_o <= "11"; elsif ((nmi_i = '1') and (rdy_i = '1')) then ld_o <= "11"; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"58") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"28") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"78") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"69" or d_i = X"65" or d_i = X"75" or d_i = X"6D" or d_i = X"7D" or d_i = X"79" or d_i = X"61" or d_i = X"71" or d_i = X"72") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"06" or d_i = X"16" or d_i = X"0E" or d_i = X"1E" or d_i (3 downto 0) = X"7" or d_i = X"14" or d_i = X"04" or d_i = X"0C" or d_i = X"1C") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70" or d_i = X"80") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"24" or d_i = X"2C" or d_i = X"3C" or d_i = X"34" or d_i = X"89") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"18") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"D8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"8F" or d_i = X"9F" or d_i = X"AF" or d_i = X"BF" or d_i = X"CF" or d_i = X"DF" or d_i = X"EF" or d_i = X"FF" or d_i = X"0F" or d_i = X"1F" or d_i = X"2F" or d_i = X"3F" or d_i = X"4F" or d_i = X"5F" or d_i = X"6F" or d_i = X"7F") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"B8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"E0" or d_i = X"E4" or d_i = X"EC") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"C0" or d_i = X"C4" or d_i = X"CC") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"C6" or d_i = X"D6" or d_i = X"CE" or d_i = X"DE") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"CA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"88") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"49" or d_i = X"45" or d_i = X"55" or d_i = X"4D" or d_i = X"5D" or d_i = X"59" or d_i = X"41" or d_i = X"51" or d_i = X"09" or d_i = X"05" or d_i = X"15" or d_i = X"0D" or d_i = X"1D" or d_i = X"19" or d_i = X"01" or d_i = X"11" or d_i = X"29" or d_i = X"25" or d_i = X"35" or d_i = X"2D" or d_i = X"3D" or d_i = X"39" or d_i = X"21" or d_i = X"31" or d_i = X"C9" or d_i = X"C5" or d_i = X"D5" or d_i = X"CD" or d_i = X"DD" or d_i = X"D9" or d_i = X"C1" or d_i = X"D1" or d_i = X"32" or d_i = X"D2" or d_i = X"52" or d_i = X"12") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"E6" or d_i = X"F6" or d_i = X"EE" or d_i = X"FE") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"E8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"C8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"4C" or d_i = X"6C" or d_i = X"7C") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"20") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"A9" or d_i = X"A5" or d_i = X"B5" or d_i = X"AD" or d_i = X"BD" or d_i = X"B9" or d_i = X"A1" or d_i = X"B1" or d_i = X"B2") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"A2" or d_i = X"A6" or d_i = X"B6" or d_i = X"AE" or d_i = X"BE") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"A0" or d_i = X"A4" or d_i = X"B4" or d_i = X"AC" or d_i = X"BC") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"46" or d_i = X"56" or d_i = X"4E" or d_i = X"5E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"EA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"48") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"08") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"7A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"26" or d_i = X"36" or d_i = X"2E" or d_i = X"3E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"66" or d_i = X"76" or d_i = X"6E" or d_i = X"7E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"40") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"60") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"E9" or d_i = X"E5" or d_i = X"F5" or d_i = X"ED" or d_i = X"FD" or d_i = X"F9" or d_i = X"E1" or d_i = X"F1" or d_i = X"F2") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"38") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"F8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"85" or d_i = X"95" or d_i = X"8D" or d_i = X"9D" or d_i = X"99" or d_i = X"81" or d_i = X"91" or d_i = X"92") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"86" or d_i = X"96" or d_i = X"8E") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"84" or d_i = X"94" or d_i = X"8C") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"AA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"0A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"4A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"2A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"6A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"A8") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"98") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"BA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"8A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"9A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"DA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"5A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"68") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"FA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"9C" or d_i = X"9E" or d_i = X"64" or d_i = X"74") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"3A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"1A") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"EA") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"02" or d_i = X"22" or d_i = X"42" or d_i = X"62" or d_i = X"82" or d_i = X"C2" or d_i = X"E2") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((d_i = X"44") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"54" or d_i = X"D4" or d_i = X"F4") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"DC" or d_i = X"FC") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"5C") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i(3 downto 0) = X"3" or d_i(3 downto 0) = X"B") and (rdy_i = '1')) then ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; end if; when s6 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s7 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s8 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s9 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s10 => if (rdy_i = '1' and zw_REG_OP = X"9A") then adr_o <= X"01" & d_regs_out_i; ld_o <= "11"; ld_sp_o <= '1'; sig_SYNC <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"BA") then d_regs_in_o <= adr_sp_i (7 downto 0); ch_a_o <= adr_sp_i (7 downto 0); ch_b_o <= X"00"; load_regs_o <= '1'; sig_SYNC <= '1'; elsif (rdy_i = '1') then ch_a_o <= d_regs_out_i; ch_b_o <= X"00"; load_regs_o <= '1'; sig_SYNC <= '1'; end if; when s13 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s18 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s19 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s26 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s27 => if (rdy_i = '1') then d_regs_in_o <= d_alu_i; ch_a_o <= d_regs_out_i; ch_b_o <= zw_b4; load_regs_o <= '1'; sig_SYNC <= '1'; end if; when s203 => if (rdy_i = '1' and (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then ld_o <= "11"; ld_pc_o <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then ld_o <= "11"; ld_pc_o <= '1'; zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; sig_SYNC <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then ld_o <= "11"; ld_pc_o <= '1'; d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"B5" OR zw_REG_OP = X"B4" OR zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR zw_REG_OP = X"35" OR zw_REG_OP = X"D5")) then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and (zw_REG_OP = X"AD" OR zw_REG_OP = X"AE" OR zw_REG_OP = X"AC" OR zw_REG_OP = X"4D" OR zw_REG_OP = X"0D" OR zw_REG_OP = X"2D" OR zw_REG_OP = X"CD" OR zw_REG_OP = X"EC" OR zw_REG_OP = X"CC")) then ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"BD" OR zw_REG_OP = X"BC" OR zw_REG_OP = X"5D" OR zw_REG_OP = X"1D" OR zw_REG_OP = X"3D" OR zw_REG_OP = X"DD")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and (zw_REG_OP = X"B9" OR zw_REG_OP = X"BE" OR zw_REG_OP = X"59" OR zw_REG_OP = X"19" OR zw_REG_OP = X"39" OR zw_REG_OP = X"D9")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; elsif (rdy_i = '1' and (zw_REG_OP = X"B1" OR zw_REG_OP = X"51" OR zw_REG_OP = X"11" OR zw_REG_OP = X"31" OR zw_REG_OP = X"D1")) then ch_a_o <= d_i; ch_b_o <= X"01"; elsif (rdy_i = '1' and (zw_REG_OP = X"A1" OR zw_REG_OP = X"41" OR zw_REG_OP = X"01" OR zw_REG_OP = X"21" OR zw_REG_OP = X"C1")) then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"B6") then ch_a_o <= d_i; ch_b_o <= q_y_i; elsif (rdy_i = '1' and (zw_REG_OP = X"32" OR zw_REG_OP = X"D2" OR zw_REG_OP = X"52" OR zw_REG_OP = X"B2" OR zw_REG_OP = X"12")) then ch_a_o <= d_i; ch_b_o <= X"01"; end if; when s204 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; end if; when s212 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; end if; when s216 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; end if; when s219 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; end if; when s227 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; end if; when s228 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; end if; when s230 => if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; sig_SYNC <= '1'; elsif (rdy_i = '1') then d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when s231 => if ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then d_regs_in_o <= d_i OR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i OR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then d_regs_in_o <= d_i XOR q_a_i; load_regs_o <= '1'; ch_a_o <= d_i XOR q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then d_regs_in_o <= d_i AND q_a_i; load_regs_o <= '1'; ch_a_o <= d_i AND q_a_i; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif ((rdy_i = '1' AND zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then zw_ALU (8 downto 0) <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; sig_SYNC <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0') then d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when s512 => ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"65") then ld_o <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '0') then ld_o <= "11"; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"75") then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"6D") then ld_o <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"7D") then ld_o <= "11"; ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"79") then ld_o <= "11"; ch_a_o <= d_i; ch_b_o <= q_y_i; elsif (rdy_i = '1' and zw_REG_OP = X"71") then ch_a_o <= d_i; ch_b_o <= X"01"; elsif (rdy_i = '1' and zw_REG_OP = X"61") then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"69" and reg_F(3) = '1') then ld_o <= "11"; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5)); zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; zw_ALU4(4) <= zw_ALU5(4) OR (zw_ALU5(3) AND zw_ALU5(2)) OR (zw_ALU5(3) AND zw_ALU5(1)); zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4)); zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; zw_ALU3(4) <= zw_ALU1(4) OR (zw_ALU1(3) AND zw_ALU1(2)) OR (zw_ALU1(3) AND zw_ALU1(1)); zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); elsif (rdy_i = '1' and zw_REG_OP = X"72") then ch_a_o <= d_i; ch_b_o <= X"01"; end if; when s554 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s578 => ld_pc_o <= '1'; if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; end if; when s581 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; end if; when s582 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s584 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; end if; when s585 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5)); zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; zw_ALU4(4) <= zw_ALU5(4) OR (zw_ALU5(3) AND zw_ALU5(2)) OR (zw_ALU5(3) AND zw_ALU5(1)); zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4)); zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; zw_ALU3(4) <= zw_ALU1(4) OR (zw_ALU1(3) AND zw_ALU1(2)) OR (zw_ALU1(3) AND zw_ALU1(1)); zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); end if; when s586 => if (rdy_i = '1' and reg_F(3) = '0') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); sig_SYNC <= '1'; elsif (rdy_i = '1' and reg_F(3) = '1') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_ALU5(3 downto 0)) + unsigned (zw_ALU4(8 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU3(8 downto 5)); zw_ALU4(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; zw_ALU4(4) <= zw_ALU5(4) OR (zw_ALU5(3) AND zw_ALU5(2)) OR (zw_ALU5(3) AND zw_ALU5(1)); zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU3(4)); zw_ALU3(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; zw_ALU3(4) <= zw_ALU1(4) OR (zw_ALU1(3) AND zw_ALU1(2)) OR (zw_ALU1(3) AND zw_ALU1(1)); zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0); end if; when s587 => ld_pc_o <= '1'; if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; end if; when s178 => if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"64" OR zw_REG_OP = X"84")) then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"74" OR zw_REG_OP = X"94")) then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"9C" OR zw_REG_OP = X"8C")) then ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"9D" OR zw_REG_OP = X"9E")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"99") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_y_i; elsif (rdy_i = '1' and zw_REG_OP = X"91") then ch_a_o <= d_i; ch_b_o <= X"01"; elsif (rdy_i = '1' and zw_REG_OP = X"81") then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"96") then ch_a_o <= d_i; ch_b_o <= q_y_i; elsif (rdy_i = '1' and zw_REG_OP = X"92") then ch_a_o <= d_i; ch_b_o <= X"01"; end if; when s194 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; end if; when s195 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; end if; when s196 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; end if; when s197 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s198 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; end if; when s200 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s205 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; end if; when s206 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; end if; when s207 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s208 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; end if; when s209 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_pc_o <= '1'; end if; when s213 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s513 => ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"E5") then ld_o <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '0') then ld_o <= "11"; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"F5") then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"ED") then ld_o <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"FD") then ld_o <= "11"; ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"F9") then ld_o <= "11"; ch_a_o <= d_i; ch_b_o <= q_y_i; elsif (rdy_i = '1' and zw_REG_OP = X"F1") then ch_a_o <= d_i; ch_b_o <= X"01"; elsif (rdy_i = '1' and zw_REG_OP = X"E1") then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"E9" and reg_F(3) = '1') then ld_o <= "11"; d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) - unsigned (zw_ALU6(7 downto 0)); zw_ALU6(7 downto 0) <= '0' & (NOT zw_ALU2(4)) & (NOT zw_ALU2(4)) & '0' & '0' & (NOT zw_ALU1(4)) & (NOT zw_ALU1(4)) & '0'; zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) + (zw_ALU1(4)); zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) + reg_F(0); elsif (rdy_i = '1' and zw_REG_OP = X"F2") then ch_a_o <= d_i; ch_b_o <= X"01"; end if; when s588 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s589 => ld_pc_o <= '1'; if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; end if; when s590 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= q_y_i; end if; when s591 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s593 => ld_pc_o <= '1'; if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= X"01"; ld_o <= "11"; end if; when s594 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"01"; end if; when s595 => if (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '0') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; elsif (rdy_i = '1' AND zw_b2(0) = '0' and reg_F(3) = '1') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) - unsigned (zw_ALU6(7 downto 0)); zw_ALU6(7 downto 0) <= '0' & (NOT zw_ALU2(4)) & (NOT zw_ALU2(4)) & '0' & '0' & (NOT zw_ALU1(4)) & (NOT zw_ALU1(4)) & '0'; zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) + (zw_ALU1(4)); zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) + reg_F(0); end if; when s596 => if (rdy_i = '1' and reg_F(3) = '0') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); sig_SYNC <= '1'; elsif (rdy_i = '1' and reg_F(3) = '1') then d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 0) <= unsigned (( zw_ALU2(3 downto 0)) & ( zw_ALU1(3 downto 0))) - unsigned (zw_ALU6(7 downto 0)); zw_ALU6(7 downto 0) <= '0' & (NOT zw_ALU2(4)) & (NOT zw_ALU2(4)) & '0' & '0' & (NOT zw_ALU1(4)) & (NOT zw_ALU1(4)) & '0'; zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + unsigned ("00" & NOT (d_i(7 downto 4))) + (zw_ALU1(4)); zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + unsigned ("00" & NOT (d_i(3 downto 0))) + reg_F(0); end if; when s405 => if (rdy_i = '1' and (zw_REG_OP = X"1E" or zw_REG_OP = X"7E" or zw_REG_OP = X"3E" or zw_REG_OP = X"5E")) then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"66" or zw_REG_OP = X"26" or zw_REG_OP = X"46" or zw_REG_OP = X"04" or zw_REG_OP = X"14")) then ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and (zw_REG_OP = X"16" or zw_REG_OP = X"76" or zw_REG_OP = X"36" or zw_REG_OP = X"56")) then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and (zw_REG_OP = X"0E" or zw_REG_OP = X"6E" or zw_REG_OP = X"2E" or zw_REG_OP = X"4E"or zw_REG_OP = X"0C" or zw_REG_OP = X"1C")) then ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and zw_REG_OP (3 downto 0) = X"7") then ld_o <= "11"; ld_pc_o <= '1'; end if; when s408 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; end if; when s410 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; end if; when s411 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; end if; when s417 => if ((rdy_i = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) and (rdy_i = '1')) then sig_D_OUT <= d_i(6 downto 0) & '0'; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) and (rdy_i = '1')) then sig_D_OUT <= '0' & d_i(7 downto 1); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) and (rdy_i = '1')) then sig_D_OUT <= d_i(6 downto 0) & reg_F(0); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) and (rdy_i = '1')) then sig_D_OUT <= reg_F(0) & d_i(7 downto 1); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and zw_REG_OP (7) = '0' and zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then sig_D_OUT <= d_i and NOT (d_alu_prio_i); ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and zw_REG_OP (7) = '1' and zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then sig_D_OUT <= d_i or d_alu_prio_i; ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"14" or zw_REG_OP = X"1C")) and (rdy_i = '1')) then sig_D_OUT <= d_i and NOT (q_a_i); sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; elsif ((rdy_i = '1' and (zw_REG_OP = X"04" or zw_REG_OP = X"0C")) and (rdy_i = '1')) then sig_D_OUT <= d_i or q_a_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; end if; when s419 => if ((zw_REG_OP (3 downto 0) = X"7") and (rdy_i = '1')) then sig_SYNC <= '1'; elsif (((zw_REG_OP = X"14" or zw_REG_OP = X"04" or zw_REG_OP = X"0C" or zw_REG_OP = X"1C")) and (rdy_i = '1')) then ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when s420 => if (rdy_i = '1') then ch_a_o <= q_a_i (6 downto 0) & '0'; ch_b_o <= X"00"; d_regs_in_o <= q_a_i (6 downto 0) & '0'; load_regs_o <= '1'; sig_SYNC <= '1'; end if; when s598 => if (rdy_i = '1') then ch_a_o <= reg_F(0) & q_a_i (7 downto 1); ch_b_o <= X"00"; d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1); load_regs_o <= '1'; sig_SYNC <= '1'; end if; when s599 => if (rdy_i = '1') then ch_a_o <= '0' & q_a_i (7 downto 1); ch_b_o <= X"00"; d_regs_in_o <= '0' & q_a_i (7 downto 1); load_regs_o <= '1'; sig_SYNC <= '1'; end if; when s600 => if (rdy_i = '1') then ch_a_o <= q_a_i (6 downto 0) & reg_F(0); ch_b_o <= X"00"; d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0); load_regs_o <= '1'; sig_SYNC <= '1'; end if; when s268 => ld_pc_o <= '1'; if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when s305 => offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_pc_o <= '1'; if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when s306 => offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); if (rdy_i = '1') then sig_SYNC <= '1'; end if; when jmp1 => ld_pc_o <= '1'; when jmp2_1 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; end if; when jmp_ex => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; sig_SYNC <= '1'; end if; when jmp2_2 => offset_o <= (X"00" & q_x_i); ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; end if; when s402 => ld_sp_o <= '1'; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s421 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (15 downto 8); end if; when s422 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_pc_i (7 downto 0); end if; when s424 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; sig_SYNC <= '1'; end if; when s362 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; end if; when s221 => if (rdy_i = '1' and zw_REG_OP = X"34") then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"3C") then ld_o <= "11"; ld_pc_o <= '1'; ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and zw_REG_OP = X"24") then ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"2C") then ld_o <= "11"; ld_pc_o <= '1'; elsif (rdy_i = '1' and zw_REG_OP = X"89") then ch_a_o <= q_a_i AND d_i; ch_b_o <= X"00"; ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; end if; when s232 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; ld_pc_o <= '1'; end if; when s233 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; end if; when s234 => if (rdy_i = '1') then ch_a_o <= q_a_i AND d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when s235 => if (rdy_i = '1' AND zw_b2(0) = '0') then ch_a_o <= q_a_i AND d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when brk1 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_nxt_pc_i (15 downto 8); end if; when brk2 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= adr_nxt_pc_i (7 downto 0); end if; when brk3 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F OR X"30"; end if; when brk6 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; sig_SYNC <= '1'; end if; when s425 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s426 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s427 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s429 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; sig_SYNC <= '1'; end if; when s430 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s431 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s433 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; ld_o <= "11"; end if; when s434 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s236 => ld_pc_o <= '1'; if (rdy_i = '1' and (zw_REG_OP = X"C6" OR zw_REG_OP = X"E6")) then ld_o <= "11"; elsif (rdy_i = '1' and (zw_REG_OP = X"D6" OR zw_REG_OP = X"F6")) then ch_a_o <= d_i; ch_b_o <= q_x_i; elsif (rdy_i = '1' and (zw_REG_OP = X"CE" OR zw_REG_OP = X"EE")) then ld_o <= "11"; elsif (rdy_i = '1' and (zw_REG_OP = X"DE" OR zw_REG_OP = X"FE")) then ld_o <= "11"; ch_a_o <= d_i; ch_b_o <= q_x_i; end if; when s245 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s246 => ld_pc_o <= '1'; if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= "0000000" & zw_b2(0); ld_o <= "11"; end if; when s248 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s346 => if (rdy_i = '1') then ch_a_o <= d_i; ch_b_o <= zw_b4; end if; when s252 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b1; end if; when s253 => if (rdy_i = '1') then ch_a_o <= zw_b1; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when s435 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_o <= "11"; ld_sp_o <= '1'; end if; when s436 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s437 => if (rdy_i = '1') then sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F OR X"30"; ld_o <= "11"; ld_sp_o <= '1'; end if; when s438 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s439 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; end if; when s441 => if (rdy_i = '1') then d_regs_in_o <= d_i; load_regs_o <= '1'; ch_a_o <= d_i; ch_b_o <= X"00"; sig_SYNC <= '1'; end if; when s442 => if (rdy_i = '1') then ld_o <= "11"; ld_sp_o <= '1'; end if; when s444 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when irq1 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_w3 (15 downto 8); end if; when irq2 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_w3 (7 downto 0); end if; when irq3 => ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= (reg_F AND X"EF"); end if; when irq6 => ld_pc_o <= '1'; if (rdy_i = '1') then adr_o <= d_i & zw_b1; rst_nmi_o <= '1'; ld_o <= "11"; sig_SYNC <= '1'; end if; when s11 => if (rdy_i = '1') then ld_o <= "11"; ld_pc_o <= '1'; sig_SYNC <= '1'; end if; when s12 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s20 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s14 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s23 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s15 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s25 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s28 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s16 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s30 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s33 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when jmp3_2 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s601 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s602 => if (rdy_i = '1') then sig_SYNC <= '1'; end if; when s270 => ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when s307 => offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_pc_o <= '1'; if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when s308 => ld_pc_o <= '1'; if (rdy_i = '1' and ( (zw_b1(0) = '0' and zw_REG_OP = X"8F") or (zw_b1(1) = '0' and zw_REG_OP = X"9F") or (zw_b1(2) = '0' and zw_REG_OP = X"AF") or (zw_b1(3) = '0' and zw_REG_OP = X"BF") or (zw_b1(4) = '0' and zw_REG_OP = X"CF") or (zw_b1(5) = '0' and zw_REG_OP = X"DF") or (zw_b1(6) = '0' and zw_REG_OP = X"EF") or (zw_b1(7) = '0' and zw_REG_OP = X"FF") or (zw_b1(0) = '1' and zw_REG_OP = X"0F") or (zw_b1(1) = '1' and zw_REG_OP = X"1F") or (zw_b1(2) = '1' and zw_REG_OP = X"2F") or (zw_b1(3) = '1' and zw_REG_OP = X"3F") or (zw_b1(4) = '1' and zw_REG_OP = X"4F") or (zw_b1(5) = '1' and zw_REG_OP = X"5F") or (zw_b1(6) = '1' and zw_REG_OP = X"6F") or (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when s309 => offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); if (rdy_i = '1') then sig_SYNC <= '1'; end if; when RES7 => ld_o <= "11"; ld_pc_o <= '1'; ld_sp_o <= '1'; sig_RWn <= '1'; sig_RD <= '1'; when others => null; end case; end process output_proc; -- Concurrent Statements -- Clocked output assignments d_o <= d_o_cld; rd_o <= rd_o_cld; sync_o <= sync_o_cld; wr_n_o <= wr_n_o_cld; wr_o <= wr_o_cld; end fsm;