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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity fsm_execution_unit is port( adr_nxt_pc_i : in std_logic_vector (15 downto 0); adr_pc_i : in std_logic_vector (15 downto 0); adr_sp_i : in std_logic_vector (15 downto 0); clk_clk_i : in std_logic; d_alu_i : in std_logic_vector ( 7 downto 0 ); d_alu_prio_i : in std_logic_vector (7 downto 0); d_i : in std_logic_vector ( 7 downto 0 ); d_regs_out_i : in std_logic_vector ( 7 downto 0 ); irq_n_i : in std_logic; nmi_i : in std_logic; q_a_i : in std_logic_vector ( 7 downto 0 ); q_x_i : in std_logic_vector ( 7 downto 0 ); q_y_i : in std_logic_vector ( 7 downto 0 ); rdy_i : in std_logic; reg_0flag_i : in std_logic; reg_1flag_i : in std_logic; reg_7flag_i : in std_logic; rst_rst_n_i : in std_logic; so_n_i : in std_logic; a_o : out std_logic_vector (15 downto 0); adr_o : out std_logic_vector (15 downto 0); ch_a_o : out std_logic_vector ( 7 downto 0 ); ch_b_o : out std_logic_vector ( 7 downto 0 ); d_o : out std_logic_vector ( 7 downto 0 ); d_regs_in_o : out std_logic_vector ( 7 downto 0 ); ld_o : out std_logic_vector ( 1 downto 0 ); ld_pc_o : out std_logic; ld_sp_o : out std_logic; load_regs_o : out std_logic; offset_o : out std_logic_vector ( 15 downto 0 ); rd_o : out std_logic; rst_nmi_o : out std_logic; sel_pc_in_o : out std_logic; sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); sel_reg_o : out std_logic_vector ( 1 downto 0 ); sel_sp_as_o : out std_logic; sel_sp_in_o : out std_logic; sync_o : out std_logic; wr_n_o : out std_logic; wr_o : out std_logic ); -- Declarations end fsm_execution_unit ; -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.15 2021/01/22 13:24:00 jens -- Production Release -- -- Revision 1.14 2021/01/10 17:56:00 jens -- - Performance improvements -- Revision 1.13 2018/10/14 11:50:00 jens -- - Performance improvements -- Revision 1.1202 2018/09/10 12:14:00 jens -- - RESET generates SYNC now, 1 dead cycle delayed -- Revision 1.1202 RC 2018/09/09 03:00:00 jens -- - ADC / SBC flags and A like R65C02 now -- Revision 1.1202 BETA 2018/09/05 19:35:00 jens -- - BBRx/BBSx internal cycles like real 65C02 now -- - Bug Fix ADC and SBC in decimal mode (all op codes - -- 1 cycle is missing -- - Bug Fix ADC and SBC in decimal mode (all op codes - -- "Overflow" flag was computed wrong) -- Revision 1.1202 BETA 2018/09/02 18:49:00 jens -- - Interrupt NMI and IRQ processing via FETCH stage now -- Revision 1.1202 BETA 2018/08/30 15:39:00 jens -- - Interrupt priority order is now: BRQ - NMI - IRQ -- - Performance improvements on-going (Mealy -> Moore) -- Revision 1.1202 BETA 2018/08/23 20:27:00 jens -- - Bug Fixes All Branch Instructions -- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) -- 3 cycles now if branch forward occur and the branch -- instruction lies on a xxFEh location. -- (BBR, BBS) 6 cycles now if branch forward occur and the -- branch instruction lies on a xxFDh location. -- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now -- - Bug Fix Now all cycles are delayable (WR and internal) -- -- Revision 1.1201 BETA 2014/04/19 14:44:00 jens -- (never submitted to opencores) -- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. -- When the ABS address data bytes cross the page -- boundary (e.g. $02FE JMP hhll reads hh from -- $02FF and ll from $0200, instead $02FF and $0300) -- -- Revision 1.12 RC 2013/07/31 11:53:00 jens -- - Bug Fix CMP (IND) - wrongly decoded as function AND -- - Bug Fix BRK should clear decimal flag P Reg -- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address -- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created -- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) -- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed -- - Bug Fix RTI - should increment stack pointer (decremented) -- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. -- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong) -- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. -- -- Revision 1.11 2013/07/21 11:11:00 jens -- - Changing the title block and internal revision history -- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) -- -- Revision 1.10 2010/02/08 17:34:20 eda -- BUGFIX for IRQn, NMIn and RTI -- After detection of NMI or IRQ the address of the next instruction stacked wrong. -- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the -- vector address is not loaded yet. -- -- -- Revision 1.9 2010/02/08 17:32:19 eda -- BUGFIX for IRQn, NMIn and RTI -- After detection of NMI or IRQ the address of the next instruction stacked wrong. -- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the -- vector address is not loaded yet. -- -- -- Revision 1.8 2009/01/04 20:23:42 eda -- *** EMERGENCY BUGFIX *** -- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. -- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist -- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from -- $02FF and $0200, instead of $02FF and $0300) -- -- Revision 1.7 2009/01/04 16:54:59 eda -- - Removed unused bits in ALU (zw_ALUx) -- -- Revision 1.6 2009/01/04 10:27:49 eda -- Changes for cosmetic issues only -- -- Revision 1.5 2009/01/04 10:25:04 eda -- Changes for cosmetic issues only -- -- Revision 1.4 2009/01/03 16:53:01 eda -- - Unused nets and blocks deleted -- - Re-arragend symbols in block FSM_Execution_Unit -- - Renamed blocks -- - Input SO implemented -- -- Revision 1.3 2009/01/03 16:42:02 eda -- - Unused nets and blocks deleted -- - Re-arragend symbols in block FSM_Execution_Unit -- - Renamed blocks -- - Input SO implemented -- -- Revision 1.2 2008/12/31 19:31:24 eda -- Production Release -- -- -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.13 2021/01/22 13:23:00 jens -- Production Release -- Revision 1.1207 2021/01/05 23:36:00 jens -- - Bug Fixes RDY (='0') -- - Performance improvements -- Revision 1.02 2020/12/31 17:22:00 jens -- - Bug Fix RDY (='0') forces A, X, Y and flags -- to be comulated at specific states on several -- instructions. -- Revision 1.01 2018/10/14 11:57:00 jens -- Initial Version -- -- -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.01 2018/09/26 11:11:00 jens -- Production Release -- -- -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.01 2018/09/26 11:11:00 jens -- Production Release -- -- -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.01 2018/09/26 11:11:00 jens -- Production Release -- -- -- (C) 2008 - 2021 Jens Gutschmidt -- (email: opencores@vivare-services.com) -- -- Versions: -- Revision 1.01 2018/10/02 10:36:00 jens -- Production Release -- -- -- -- r65c02_tc.fsm_execution_unit.fsm -- -- Date: 22.01.2021 -- Time: 14:49:40 -- By: VIVARE GmbH, Switzerland -- -- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- -- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; architecture fsm of fsm_execution_unit is -- Architecture Declarations signal adc_sbc_finished : std_logic; signal c_detect_out : std_logic; signal cnz_detect_in : std_logic_vector(8 DOWNTO 0); signal d_regs_out_bak_i : std_logic_vector( 7 DOWNTO 0 ); signal irq_finished : std_logic; signal n_detect_out : std_logic; signal op_fetch : std_logic; signal op_finished : std_logic; signal op_finished_det : std_logic; signal q_a_bak_i : std_logic_vector( 7 DOWNTO 0 ); signal q_x_bak_i : std_logic_vector( 7 DOWNTO 0 ); signal q_y_bak_i : std_logic_vector( 7 DOWNTO 0 ); signal reg_F : std_logic_vector( 7 DOWNTO 0 ); signal reg_F_bak : std_logic_vector( 7 DOWNTO 0 ); signal reg_op_finished : std_logic; signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); signal rmb_started : std_logic; signal rst_finished : std_logic; signal sel_pc_in : std_logic; signal sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); signal sel_sp_as : std_logic; signal sel_sp_in : std_logic; signal shift_rot_asl_out : std_logic_vector( 7 DOWNTO 0 ); signal shift_rot_in : std_logic_vector( 7 DOWNTO 0 ); signal shift_rot_l_c_out : std_logic; signal shift_rot_lsr_out : std_logic_vector( 7 DOWNTO 0 ); signal shift_rot_r_c_out : std_logic; signal shift_rot_rol_out : std_logic_vector( 7 DOWNTO 0 ); signal shift_rot_ror_out : std_logic_vector( 7 DOWNTO 0 ); signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); signal sig_PC : std_logic_vector(15 DOWNTO 0); signal sig_RD : std_logic; signal sig_RWn : std_logic; signal sig_SYNC : std_logic; signal sig_WR : std_logic; signal z_detect_out : std_logic; signal zw_ALU : std_logic_vector(9 DOWNTO 0); signal zw_ALU1 : std_logic_vector(9 DOWNTO 0); signal zw_ALU2 : std_logic_vector(9 DOWNTO 0); signal zw_ALU3 : std_logic_vector(9 DOWNTO 0); signal zw_ALU4 : std_logic_vector(9 DOWNTO 0); signal zw_ALU5 : std_logic_vector(9 DOWNTO 0); signal zw_ALU6 : std_logic_vector(9 DOWNTO 0); signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b10 : std_logic_vector(9 DOWNTO 0); signal zw_b11 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b12 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b13 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b14 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b5 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b6 : std_logic_vector( 7 DOWNTO 0 ); signal zw_b7 : std_logic_vector(9 DOWNTO 0); signal zw_b8 : std_logic_vector(9 DOWNTO 0); signal zw_b9 : std_logic_vector(9 DOWNTO 0); signal zw_din : std_logic_vector(7 DOWNTO 0); signal zw_reg_0flag : std_logic; signal zw_so : std_logic; signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); type csm_state_type is ( res2, res4, res5, res6, res7, res3, RES, FETCH, nop1, txs1, bxx1, bxx2, bxx3, jmp1, jmp2_1, jmp4_12, jmp_ex, jmp2_2, jmp3_1, jsr1, jsr2, jsr3, jsr4, jsr5, brk1, brk2, brk3, brk4, brk6, brk5, rti1, rti2, rti3, rti4, rti5, rts1, rts2, rts3, rts4, rts5, pha1, pha2, php1, php2, pla1, pla2, pla3, plp1, plp2, plp3, irq1, irq2, irq3, irq5b, irq5a, irq4, irq6a, nop22, nop231, nop232, nop241, nop242, nop243, nop341, nop342, nop343, nop381, nop382, nop383, nop384, nop387, nop385, nop386, jmp3_2, bbr1, bbr5, bbr4, bbr2, bbr3, bbr6, RES0, zp1, zp2, zpx1, zpx2, zpx3, ab1, ab2, ab3, absx1, absx2, absx4, absx3, ind1, ind3, ind4, ind2, indy1, indy2, indy3, indy5, indy4, indx1, indx4, indx2, indx3, indx5, zpy1, zpy2, zpy3, absy2, absy1, absy4, absy3, imm1, imp1, irq6b, absx5, absy5, indy6, zprmw1, zprmw2, zprmw31, zprmw41, zpxrmw1, zpxrmw2, zpxrmw3, zpxrmw41, zpxrmw51, abrmw1, abrmw2, abrmw3, abrmw41, abrmw51, abxrmb1, abxrmb2, abxrmb3, abxrmb41, abxrmb51, abxrmb61, zp2w, zpx3w, zpy3w, ab3w, absx4w, absx3w, absy4w, absy3w, ind4w, indx5w, indy5w, indy4w, zprmw32, zpxrmw42, abrmw42, abxrmb52, abxrmb42, zp3, zpx4, ab4, ind5, indx6, imm2 ); type csm_functions_state_type is ( f_idle, f_and, f_lda, f_rst, f_eor, f_cmp, f_ora, f_clc, f_sec, f_cld, f_sed, f_clv, f_cli, f_sei, f_rti, f_irq, f_res, f_bit1, f_bit2, f_de_in_a, f_adc_bin, f_sbc_bin, f_adc_dec, f_adc_dec1, f_sbc_dec, f_sbc_dec1, f_asla, f_lsra, f_rola, f_rora, f_tax, f_tsx, f_decr, f_asl, f_lsr, f_rol, f_ror, f_rmb, f_smb, f_trb, f_tsb ); type csm_rb_out_state_type is ( rb_out_idle, rb_out_01, rb_out_10, rb_out_11 ); type csm_reg_state_type is ( reg_idle, reg_10, reg_11, reg_01 ); type csm_rb_in_state_type is ( rb_in_idle, rb_in_01, rb_in_10, rb_in_00 ); type csm_add_value_state_type is ( add_val_idle, add_val ); -- Declare current and next state signals signal csm_current_state : csm_state_type; signal csm_next_state : csm_state_type; signal csm_functions_current_state : csm_functions_state_type; signal csm_functions_next_state : csm_functions_state_type; signal csm_rb_out_current_state : csm_rb_out_state_type; signal csm_rb_out_next_state : csm_rb_out_state_type; signal csm_reg_current_state : csm_reg_state_type; signal csm_reg_next_state : csm_reg_state_type; signal csm_rb_in_current_state : csm_rb_in_state_type; signal csm_rb_in_next_state : csm_rb_in_state_type; signal csm_add_value_current_state : csm_add_value_state_type; signal csm_add_value_next_state : csm_add_value_state_type; -- Declare any pre-registered internal signals signal sync_o_cld : std_logic ; begin ----------------------------------------------------------------- csm_clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then csm_current_state <= RES; -- Default Reset Values sync_o_cld <= '0'; reg_op_finished <= '0'; reg_sel_rb_in <= "00"; reg_sel_rb_out <= "00"; reg_sel_reg <= "00"; zw_PC <= X"0000"; zw_REG_ALU <= '0' & X"00"; zw_REG_OP <= X"00"; zw_REG_sig_PC <= X"0000"; zw_b1 <= X"00"; zw_b11 <= X"00"; zw_b12 <= X"00"; zw_b2 <= X"00"; zw_b3 <= X"00"; zw_b5 <= X"00"; zw_b6 <= X"00"; zw_reg_0flag <= '0'; zw_so <= '0'; zw_w1 <= X"0000"; zw_w2 <= X"0000"; zw_w3 <= X"0000"; elsif (clk_clk_i'event and clk_clk_i = '1') then csm_current_state <= csm_next_state; -- Default Assignment To Internals reg_op_finished <= op_finished; reg_sel_rb_in <= reg_sel_rb_in; reg_sel_rb_out <= reg_sel_rb_out; reg_sel_reg <= reg_sel_reg; zw_PC <= zw_PC; zw_REG_ALU <= zw_REG_ALU; zw_REG_OP <= zw_REG_OP; zw_REG_sig_PC <= zw_REG_sig_PC; zw_b1 <= zw_b1; zw_b11 <= zw_b11; zw_b12 <= zw_b12; zw_b2 <= zw_b2; zw_b3 <= zw_b3; zw_b5 <= zw_b5; zw_b6 <= zw_b6; zw_reg_0flag <= zw_reg_0flag; zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); zw_w1 <= zw_w1; zw_w2 <= zw_w2; zw_w3 <= zw_w3; sync_o_cld <= sig_SYNC; -- Combined Actions case csm_current_state is when res6 => zw_b5 <= d_i; when FETCH => zw_REG_OP <= d_i; if ((d_i = X"00") and (rdy_i = '1')) then elsif ((nmi_i = '1') and (rdy_i = '1')) then zw_w3 <= adr_pc_i; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then zw_w3 <= adr_pc_i; end if; when bxx1 => zw_b3 <= adr_nxt_pc_i (15 downto 8); zw_b2 <= d_i; when jmp1 => zw_b5 <= d_i; when jmp2_1 => zw_b6 <= d_i; when jmp4_12 => zw_b5 <= d_i; when jmp2_2 => zw_b6 <= d_i; when jsr1 => zw_b1 <= d_i; when jsr2 => zw_b11 <= adr_pc_i (15 downto 8); zw_b12 <= adr_pc_i (7 downto 0); when brk1 => zw_b11 <= adr_nxt_pc_i (15 downto 8); zw_b12 <= adr_nxt_pc_i (7 downto 0); when brk3 => zw_b11 <= reg_F OR X"30"; when brk5 => zw_b5 <= d_i; when rti4 => zw_b5 <= d_i; when rts3 => zw_b5 <= d_i; when rts4 => zw_b6 <= d_i; when irq1 => zw_b11 <= zw_w3 (15 downto 8); zw_b12 <= zw_w3 (7 downto 0); when irq3 => zw_b11 <= reg_F AND X"EF"; when irq5b => zw_b5 <= d_i; when irq5a => zw_b5 <= d_i; when bbr1 => zw_b2 <= d_i; when bbr4 => zw_w3 <= adr_pc_i; zw_b2 <= d_i; zw_b3 <= adr_nxt_pc_i (15 downto 8); when bbr3 => zw_b1 <= d_i; when zp1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when zpx1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when zpx2 => zw_b1 <= d_alu_i; when ab1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when ab2 => zw_b6 <= d_i; when absx1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when absx2 => zw_b6 <= d_i; zw_b1 <= d_alu_i; zw_reg_0flag <= reg_0flag_i; when absx3 => zw_b3 <= d_alu_i; when ind1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when ind3 => zw_b5 <= d_i; when ind2 => zw_b1 <= d_alu_i; zw_b6 <= d_i; when indy1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when indy2 => zw_b2 <= d_i; zw_b1 <= d_alu_i; when indy3 => zw_b5 <= d_i; zw_b6 <= d_alu_i; zw_reg_0flag <= reg_0flag_i; when indy4 => zw_b3 <= d_alu_i; when indx1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when indx4 => zw_b2 <= d_i; when indx2 => zw_b1 <= d_alu_i; when indx3 => zw_b5 <= d_i; zw_b6 <= d_alu_i; when zpy1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when zpy2 => zw_b1 <= d_alu_i; when absy2 => zw_b6 <= d_i; zw_b1 <= d_alu_i; zw_reg_0flag <= reg_0flag_i; when absy1 => zw_b5 <= d_i; zw_b11 <= d_regs_out_i; when absy3 => zw_b3 <= d_alu_i; when zprmw1 => zw_b5 <= d_i; when zprmw2 => zw_b2 <= d_i; when zprmw31 => zw_b11 <= d_alu_i; when zpxrmw1 => zw_b5 <= d_i; when zpxrmw2 => zw_b1 <= d_alu_i; when zpxrmw3 => zw_b2 <= d_i; when zpxrmw41 => zw_b11 <= d_alu_i; when abrmw1 => zw_b5 <= d_i; when abrmw2 => zw_b6 <= d_i; when abrmw3 => zw_b2 <= d_i; when abrmw41 => zw_b11 <= d_alu_i; when abxrmb1 => zw_b5 <= d_i; when abxrmb2 => zw_b6 <= d_i; zw_b1 <= d_alu_i; zw_reg_0flag <= reg_0flag_i; when abxrmb3 => zw_b2 <= d_i; zw_b3 <= d_alu_i; when abxrmb41 => zw_b2 <= d_i; when abxrmb51 => zw_b11 <= d_alu_i; when absx3w => zw_b3 <= d_alu_i; when absy3w => zw_b3 <= d_alu_i; when indy4w => zw_b3 <= d_alu_i; when zprmw32 => zw_b11 <= zw_b13; when zpxrmw42 => zw_b11 <= zw_b13; when abrmw42 => zw_b11 <= zw_b13; when abxrmb52 => zw_b11 <= zw_b13; when others => null; end case; end if; end process csm_clocked_proc; ----------------------------------------------------------------- csm_nextstate_proc : process ( adr_nxt_pc_i, csm_current_state, d_i, irq_n_i, nmi_i, rdy_i, reg_F, zw_REG_OP, zw_b1, zw_b3, zw_reg_0flag ) ----------------------------------------------------------------- begin case csm_current_state is when res2 => if (rdy_i = '1') then csm_next_state <= res3; else csm_next_state <= res2; end if; when res4 => if (rdy_i = '1') then csm_next_state <= res5; else csm_next_state <= res4; end if; when res5 => if (rdy_i = '1') then csm_next_state <= res6; else csm_next_state <= res5; end if; when res6 => if (rdy_i = '1') then csm_next_state <= res7; else csm_next_state <= res6; end if; when res7 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= res7; end if; when res3 => if (rdy_i = '1') then csm_next_state <= res4; else csm_next_state <= res3; end if; when RES => if (rdy_i = '1') then csm_next_state <= RES0; else csm_next_state <= RES; end if; when FETCH => if ((d_i = X"00") and (rdy_i = '1')) then csm_next_state <= brk1; elsif ((nmi_i = '1') and (rdy_i = '1')) then csm_next_state <= irq1; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then csm_next_state <= irq1; elsif ((d_i = X"8F" or d_i = X"9F" or d_i = X"AF" or d_i = X"BF" or d_i = X"CF" or d_i = X"DF" or d_i = X"EF" or d_i = X"FF" or d_i = X"0F" or d_i = X"1F" or d_i = X"2F" or d_i = X"3F" or d_i = X"4F" or d_i = X"5F" or d_i = X"6F" or d_i = X"7F") and (rdy_i = '1')) then csm_next_state <= bbr1; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70" or d_i = X"80") and (rdy_i = '1')) then csm_next_state <= bxx1; elsif ((d_i = X"4C" or d_i = X"6C" or d_i = X"7C") and (rdy_i = '1')) then csm_next_state <= jmp1; elsif ((d_i = X"20") and (rdy_i = '1')) then csm_next_state <= jsr1; elsif ((d_i = X"68") and (rdy_i = '1')) then csm_next_state <= pla1; elsif ((d_i = X"FA") and (rdy_i = '1')) then csm_next_state <= pla1; elsif ((d_i = X"C6" or d_i = X"E6" or d_i = X"66" or d_i = X"06" or d_i = X"46" or d_i = X"26" or d_i (3 downto 0) = X"7" or d_i = X"14" or d_i = X"04") and (rdy_i = '1')) then csm_next_state <= zprmw1; elsif ((d_i = X"D6" or d_i = X"F6" or d_i = X"76" or d_i = X"16" or d_i = X"56" or d_i = X"36") and (rdy_i = '1')) then csm_next_state <= zpxrmw1; elsif ((d_i = X"CE" or d_i = X"EE" or d_i = X"6E" or d_i = X"0E" or d_i = X"4E" or d_i = X"2E" or d_i = X"1C" or d_i = X"0C") and (rdy_i = '1')) then csm_next_state <= abrmw1; elsif ((d_i = X"DE" or d_i = X"FE" or d_i = X"7E" or d_i = X"1E" or d_i = X"5E" or d_i = X"3E") and (rdy_i = '1')) then csm_next_state <= abxrmb1; elsif ((d_i = X"09" or d_i = X"29" or d_i = X"49" or d_i = X"69" or d_i = X"89" or d_i = X"A0" or d_i = X"A2" or d_i = X"A9" or d_i = X"C9" or d_i = X"E0" or d_i = X"C0" or d_i = X"E9") and (rdy_i = '1')) then csm_next_state <= imm1; elsif ((d_i = X"05" or d_i = X"25" or d_i = X"45" or d_i = X"65" or d_i = X"A5" or d_i = X"24" or d_i = X"C5" or d_i = X"E4" or d_i = X"C4" or d_i = X"A6" or d_i = X"A4" or d_i = X"E5" or d_i = X"85" or d_i = X"86" or d_i = X"84" or d_i = X"64") and (rdy_i = '1')) then csm_next_state <= zp1; elsif ((d_i = X"15" or d_i = X"35" or d_i = X"55" or d_i = X"75" or d_i = X"B5" or d_i = X"34" or d_i = X"D5" or d_i = X"B4" or d_i = X"F5" or d_i = X"95" or d_i = X"94" or d_i = X"74") and (rdy_i = '1')) then csm_next_state <= zpx1; elsif ((d_i = X"B6" or d_i = X"96") and (rdy_i = '1')) then csm_next_state <= zpy1; elsif ((d_i = X"6D" or d_i = X"2D" or d_i = X"2C" or d_i = X"CD" or d_i = X"CC" or d_i = X"EC" or d_i = X"4D" or d_i = X"AD" or d_i = X"AE" or d_i = X"AC" or d_i = X"0D" or d_i = X"ED" or d_i = X"8D" or d_i = X"8E" or d_i = X"8C" or d_i = X"9C") and (rdy_i = '1')) then csm_next_state <= ab1; elsif ((d_i = X"7D" or d_i = X"3D" or d_i = X"3C" or d_i = X"DD" or d_i = X"5D" or d_i = X"BD" or d_i = X"BC" or d_i = X"1D" or d_i = X"FD" or d_i = X"9D" or d_i = X"9E") and (rdy_i = '1')) then csm_next_state <= absx1; elsif ((d_i = X"79" or d_i = X"39" or d_i = X"D9" or d_i = X"5D" or d_i = X"59" or d_i = X"B9" or d_i = X"BE" or d_i = X"19" or d_i = X"F9" or d_i = X"99") and (rdy_i = '1')) then csm_next_state <= absy1; elsif ((d_i = X"72" or d_i = X"32" or d_i = X"D2" or d_i = X"59" or d_i = X"52" or d_i = X"B2" or d_i = X"12" or d_i = X"F2" or d_i = X"92") and (rdy_i = '1')) then csm_next_state <= ind1; elsif ((d_i = X"71" or d_i = X"31" or d_i = X"D1" or d_i = X"51" or d_i = X"B1" or d_i = X"11" or d_i = X"F1" or d_i = X"91") and (rdy_i = '1')) then csm_next_state <= indy1; elsif ((d_i = X"61" or d_i = X"21" or d_i = X"C1" or d_i = X"41" or d_i = X"A1" or d_i = X"01" or d_i = X"E1" or d_i = X"81") and (rdy_i = '1')) then csm_next_state <= indx1; elsif ((d_i = X"B8" or d_i = X"38" or d_i = X"18" or d_i = X"F8" or d_i = X"D8" or d_i = X"78" or d_i = X"58" or d_i = X"0A" or d_i = X"4A" or d_i = X"2A" or d_i = X"6A" or d_i = X"A8" or d_i = X"98" or d_i = X"BA" or d_i = X"8A" or d_i = X"AA" or d_i = X"C8" or d_i = X"E8" or d_i = X"1A" or d_i = X"88" or d_i = X"CA" or d_i = X"3A") and (rdy_i = '1')) then csm_next_state <= imp1; elsif ((d_i = X"7A") and (rdy_i = '1')) then csm_next_state <= pla1; elsif ((d_i = X"28") and (rdy_i = '1')) then csm_next_state <= plp1; elsif ((d_i = X"9A") and (rdy_i = '1')) then csm_next_state <= txs1; elsif ((d_i = X"60") and (rdy_i = '1')) then csm_next_state <= rts1; elsif ((d_i = X"40") and (rdy_i = '1')) then csm_next_state <= rti1; elsif ((d_i = X"08") and (rdy_i = '1')) then csm_next_state <= php1; elsif ((d_i = X"5A") and (rdy_i = '1')) then csm_next_state <= pha1; elsif ((d_i = X"DA") and (rdy_i = '1')) then csm_next_state <= pha1; elsif ((d_i = X"48") and (rdy_i = '1')) then csm_next_state <= pha1; elsif ((d_i = X"EA") and (rdy_i = '1')) then csm_next_state <= nop1; elsif ((d_i(3 downto 0) = X"3" or d_i(3 downto 0) = X"B") and (rdy_i = '1')) then csm_next_state <= FETCH; elsif ((d_i = X"02" or d_i = X"22" or d_i = X"42" or d_i = X"62" or d_i = X"82" or d_i = X"C2" or d_i = X"E2") and (rdy_i = '1')) then csm_next_state <= nop22; elsif ((d_i = X"44") and (rdy_i = '1')) then csm_next_state <= nop231; elsif ((d_i = X"54" or d_i = X"D4" or d_i = X"F4") and (rdy_i = '1')) then csm_next_state <= nop241; elsif ((d_i = X"DC" or d_i = X"FC") and (rdy_i = '1')) then csm_next_state <= nop341; elsif ((d_i = X"5C") and (rdy_i = '1')) then csm_next_state <= nop381; else csm_next_state <= FETCH; end if; when nop1 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= nop1; end if; when txs1 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= txs1; end if; when bxx1 => if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= bxx2; else csm_next_state <= bxx1; end if; when bxx2 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= bxx3; else csm_next_state <= bxx2; end if; when bxx3 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= bxx3; end if; when jmp1 => if (rdy_i = '1' and zw_REG_OP = X"4C") then csm_next_state <= jmp_ex; elsif (rdy_i = '1' and zw_REG_OP = X"6C") then csm_next_state <= jmp2_1; elsif (rdy_i = '1' and zw_REG_OP = X"7C") then csm_next_state <= jmp2_2; else csm_next_state <= jmp1; end if; when jmp2_1 => if (rdy_i = '1') then csm_next_state <= jmp3_1; else csm_next_state <= jmp2_1; end if; when jmp4_12 => if (rdy_i = '1') then csm_next_state <= jmp_ex; else csm_next_state <= jmp4_12; end if; when jmp_ex => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= jmp_ex; end if; when jmp2_2 => if (rdy_i = '1') then csm_next_state <= jmp3_2; else csm_next_state <= jmp2_2; end if; when jmp3_1 => if (rdy_i = '1') then csm_next_state <= jmp4_12; else csm_next_state <= jmp3_1; end if; when jsr1 => if (rdy_i = '1') then csm_next_state <= jsr2; else csm_next_state <= jsr1; end if; when jsr2 => if (rdy_i = '1') then csm_next_state <= jsr3; else csm_next_state <= jsr2; end if; when jsr3 => if (rdy_i = '1') then csm_next_state <= jsr4; else csm_next_state <= jsr3; end if; when jsr4 => if (rdy_i = '1') then csm_next_state <= jsr5; else csm_next_state <= jsr4; end if; when jsr5 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= jsr5; end if; when brk1 => if (rdy_i = '1') then csm_next_state <= brk2; else csm_next_state <= brk1; end if; when brk2 => if (rdy_i = '1') then csm_next_state <= brk3; else csm_next_state <= brk2; end if; when brk3 => if (rdy_i = '1') then csm_next_state <= brk4; else csm_next_state <= brk3; end if; when brk4 => if (rdy_i = '1') then csm_next_state <= brk5; else csm_next_state <= brk4; end if; when brk6 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= brk6; end if; when brk5 => if (rdy_i = '1') then csm_next_state <= brk6; else csm_next_state <= brk5; end if; when rti1 => if (rdy_i = '1') then csm_next_state <= rti2; else csm_next_state <= rti1; end if; when rti2 => if (rdy_i = '1') then csm_next_state <= rti3; else csm_next_state <= rti2; end if; when rti3 => if (rdy_i = '1') then csm_next_state <= rti4; else csm_next_state <= rti3; end if; when rti4 => if (rdy_i = '1') then csm_next_state <= rti5; else csm_next_state <= rti4; end if; when rti5 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= rti5; end if; when rts1 => if (rdy_i = '1') then csm_next_state <= rts2; else csm_next_state <= rts1; end if; when rts2 => if (rdy_i = '1') then csm_next_state <= rts3; else csm_next_state <= rts2; end if; when rts3 => if (rdy_i = '1') then csm_next_state <= rts4; else csm_next_state <= rts3; end if; when rts4 => if (rdy_i = '1') then csm_next_state <= rts5; else csm_next_state <= rts4; end if; when rts5 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= rts5; end if; when pha1 => if (rdy_i = '1') then csm_next_state <= pha2; else csm_next_state <= pha1; end if; when pha2 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= pha2; end if; when php1 => if (rdy_i = '1') then csm_next_state <= php2; else csm_next_state <= php1; end if; when php2 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= php2; end if; when pla1 => if (rdy_i = '1') then csm_next_state <= pla2; else csm_next_state <= pla1; end if; when pla2 => if (rdy_i = '1') then csm_next_state <= pla3; else csm_next_state <= pla2; end if; when pla3 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= pla3; end if; when plp1 => if (rdy_i = '1') then csm_next_state <= plp2; else csm_next_state <= plp1; end if; when plp2 => if (rdy_i = '1') then csm_next_state <= plp3; else csm_next_state <= plp2; end if; when plp3 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= plp3; end if; when irq1 => if (rdy_i = '1') then csm_next_state <= irq2; else csm_next_state <= irq1; end if; when irq2 => if (rdy_i = '1') then csm_next_state <= irq3; else csm_next_state <= irq2; end if; when irq3 => if (rdy_i = '1') then csm_next_state <= irq4; else csm_next_state <= irq3; end if; when irq5b => if (rdy_i = '1') then csm_next_state <= irq6b; else csm_next_state <= irq5b; end if; when irq5a => if (rdy_i = '1') then csm_next_state <= irq6a; else csm_next_state <= irq5a; end if; when irq4 => if (rdy_i = '1' and nmi_i = '1') then csm_next_state <= irq5a; elsif (rdy_i = '1') then csm_next_state <= irq5b; else csm_next_state <= irq4; end if; when irq6a => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= irq6a; end if; when nop22 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= nop22; end if; when nop231 => if (rdy_i = '1') then csm_next_state <= nop232; else csm_next_state <= nop231; end if; when nop232 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= nop232; end if; when nop241 => if (rdy_i = '1') then csm_next_state <= nop242; else csm_next_state <= nop241; end if; when nop242 => if (rdy_i = '1') then csm_next_state <= nop243; else csm_next_state <= nop242; end if; when nop243 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= nop243; end if; when nop341 => if (rdy_i = '1') then csm_next_state <= nop342; else csm_next_state <= nop341; end if; when nop342 => if (rdy_i = '1') then csm_next_state <= nop343; else csm_next_state <= nop342; end if; when nop343 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= nop343; end if; when nop381 => if (rdy_i = '1') then csm_next_state <= nop382; else csm_next_state <= nop381; end if; when nop382 => if (rdy_i = '1') then csm_next_state <= nop383; else csm_next_state <= nop382; end if; when nop383 => if (rdy_i = '1') then csm_next_state <= nop384; else csm_next_state <= nop383; end if; when nop384 => if (rdy_i = '1') then csm_next_state <= nop385; else csm_next_state <= nop384; end if; when nop387 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= nop387; end if; when nop385 => if (rdy_i = '1') then csm_next_state <= nop386; else csm_next_state <= nop385; end if; when nop386 => if (rdy_i = '1') then csm_next_state <= nop387; else csm_next_state <= nop386; end if; when jmp3_2 => if (rdy_i = '1') then csm_next_state <= jmp4_12; else csm_next_state <= jmp3_2; end if; when bbr1 => if (rdy_i = '1') then csm_next_state <= bbr2; else csm_next_state <= bbr1; end if; when bbr5 => if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= bbr6; else csm_next_state <= bbr5; end if; when bbr4 => if (rdy_i = '1' and ( (zw_b1(0) = '0' and zw_REG_OP = X"8F") or (zw_b1(1) = '0' and zw_REG_OP = X"9F") or (zw_b1(2) = '0' and zw_REG_OP = X"AF") or (zw_b1(3) = '0' and zw_REG_OP = X"BF") or (zw_b1(4) = '0' and zw_REG_OP = X"CF") or (zw_b1(5) = '0' and zw_REG_OP = X"DF") or (zw_b1(6) = '0' and zw_REG_OP = X"EF") or (zw_b1(7) = '0' and zw_REG_OP = X"FF") or (zw_b1(0) = '1' and zw_REG_OP = X"0F") or (zw_b1(1) = '1' and zw_REG_OP = X"1F") or (zw_b1(2) = '1' and zw_REG_OP = X"2F") or (zw_b1(3) = '1' and zw_REG_OP = X"3F") or (zw_b1(4) = '1' and zw_REG_OP = X"4F") or (zw_b1(5) = '1' and zw_REG_OP = X"5F") or (zw_b1(6) = '1' and zw_REG_OP = X"6F") or (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= bbr5; else csm_next_state <= bbr4; end if; when bbr2 => if (rdy_i = '1') then csm_next_state <= bbr3; else csm_next_state <= bbr2; end if; when bbr3 => if (rdy_i = '1') then csm_next_state <= bbr4; else csm_next_state <= bbr3; end if; when bbr6 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= bbr6; end if; when RES0 => if (rdy_i = '1') then csm_next_state <= res2; else csm_next_state <= RES0; end if; when zp1 => if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"64" OR zw_REG_OP = X"84")) then csm_next_state <= zp2w; elsif (rdy_i = '1') then csm_next_state <= zp2; else csm_next_state <= zp1; end if; when zp2 => if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"65" OR zw_REG_OP = X"E5")) then csm_next_state <= zp3; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zp2; end if; when zpx1 => if (rdy_i = '1') then csm_next_state <= zpx2; else csm_next_state <= zpx1; end if; when zpx2 => if (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"74" OR zw_REG_OP = X"94")) then csm_next_state <= zpx3w; elsif (rdy_i = '1') then csm_next_state <= zpx3; else csm_next_state <= zpx2; end if; when zpx3 => if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"75" OR zw_REG_OP = X"F5")) then csm_next_state <= zpx4; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zpx3; end if; when ab1 => if (rdy_i = '1') then csm_next_state <= ab2; else csm_next_state <= ab1; end if; when ab2 => if (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"9C" OR zw_REG_OP = X"8C")) then csm_next_state <= ab3w; elsif (rdy_i = '1') then csm_next_state <= ab3; else csm_next_state <= ab2; end if; when ab3 => if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"6D" OR zw_REG_OP = X"ED")) then csm_next_state <= ab4; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= ab3; end if; when absx1 => if (rdy_i = '1') then csm_next_state <= absx2; else csm_next_state <= absx1; end if; when absx2 => if (rdy_i = '1' and (zw_REG_OP = X"9D" OR zw_REG_OP = X"9E")) then csm_next_state <= absx3w; elsif (rdy_i = '1') then csm_next_state <= absx3; else csm_next_state <= absx2; end if; when absx4 => if ((rdy_i = '1') and ((zw_REG_OP = X"7D" or zw_REG_OP = X"FD") and reg_F(3) = '1')) then csm_next_state <= absx5; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= absx4; end if; when absx3 => if ((rdy_i = '1' AND zw_reg_0flag = '0') and ((zw_REG_OP = X"7D" or zw_REG_OP = X"FD") and reg_F(3) = '1')) then csm_next_state <= absx5; elsif (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= absx4; else csm_next_state <= absx3; end if; when ind1 => if (rdy_i = '1') then csm_next_state <= ind2; else csm_next_state <= ind1; end if; when ind3 => if (rdy_i = '1' and zw_REG_OP = X"92") then csm_next_state <= ind4w; elsif (rdy_i = '1') then csm_next_state <= ind4; else csm_next_state <= ind3; end if; when ind4 => if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"72" OR zw_REG_OP = X"F2")) then csm_next_state <= ind5; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= ind4; end if; when ind2 => if (rdy_i = '1') then csm_next_state <= ind3; else csm_next_state <= ind2; end if; when indy1 => if (rdy_i = '1') then csm_next_state <= indy2; else csm_next_state <= indy1; end if; when indy2 => if (rdy_i = '1') then csm_next_state <= indy3; else csm_next_state <= indy2; end if; when indy3 => if (rdy_i = '1' and zw_REG_OP = X"91") then csm_next_state <= indy4w; elsif (rdy_i = '1') then csm_next_state <= indy4; else csm_next_state <= indy3; end if; when indy5 => if ((rdy_i = '1') and ((zw_REG_OP = X"71" or zw_REG_OP = X"F1") and reg_F(3) = '1')) then csm_next_state <= indy6; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= indy5; end if; when indy4 => if ((rdy_i = '1' AND zw_reg_0flag = '0') and ((zw_REG_OP = X"71" or zw_REG_OP = X"F1") and reg_F(3) = '1')) then csm_next_state <= indy6; elsif (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= indy5; else csm_next_state <= indy4; end if; when indx1 => if (rdy_i = '1') then csm_next_state <= indx2; else csm_next_state <= indx1; end if; when indx4 => if (rdy_i = '1' and zw_REG_OP = X"81") then csm_next_state <= indx5w; elsif (rdy_i = '1') then csm_next_state <= indx5; else csm_next_state <= indx4; end if; when indx2 => if (rdy_i = '1') then csm_next_state <= indx3; else csm_next_state <= indx2; end if; when indx3 => if (rdy_i = '1') then csm_next_state <= indx4; else csm_next_state <= indx3; end if; when indx5 => if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"61" OR zw_REG_OP = X"E1")) then csm_next_state <= indx6; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= indx5; end if; when zpy1 => if (rdy_i = '1') then csm_next_state <= zpy2; else csm_next_state <= zpy1; end if; when zpy2 => if (rdy_i = '1' and zw_REG_OP = X"96") then csm_next_state <= zpy3w; elsif (rdy_i = '1') then csm_next_state <= zpy3; else csm_next_state <= zpy2; end if; when zpy3 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zpy3; end if; when absy2 => if (rdy_i = '1' and zw_REG_OP = X"99") then csm_next_state <= absy3w; elsif (rdy_i = '1') then csm_next_state <= absy3; else csm_next_state <= absy2; end if; when absy1 => if (rdy_i = '1') then csm_next_state <= absy2; else csm_next_state <= absy1; end if; when absy4 => if ((rdy_i = '1') and ((zw_REG_OP = X"79" or zw_REG_OP = X"F9") and reg_F(3) = '1')) then csm_next_state <= absy5; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= absy4; end if; when absy3 => if ((rdy_i = '1' AND zw_reg_0flag = '0') and ((zw_REG_OP = X"79" or zw_REG_OP = X"F9") and reg_F(3) = '1')) then csm_next_state <= absy5; elsif (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= absy4; else csm_next_state <= absy3; end if; when imm1 => if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"69" OR zw_REG_OP = X"E9")) then csm_next_state <= imm2; elsif (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= imm1; end if; when imp1 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= imp1; end if; when irq6b => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= irq6b; end if; when absx5 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= absx5; end if; when absy5 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= absy5; end if; when indy6 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= indy6; end if; when zprmw1 => if (rdy_i = '1') then csm_next_state <= zprmw2; else csm_next_state <= zprmw1; end if; when zprmw2 => if (rdy_i = '1' and (zw_REG_OP = X"C6" or zw_REG_OP = X"E6")) then csm_next_state <= zprmw31; elsif (rdy_i = '1') then csm_next_state <= zprmw32; else csm_next_state <= zprmw2; end if; when zprmw31 => if (rdy_i = '1') then csm_next_state <= zprmw41; else csm_next_state <= zprmw31; end if; when zprmw41 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zprmw41; end if; when zpxrmw1 => if (rdy_i = '1') then csm_next_state <= zpxrmw2; else csm_next_state <= zpxrmw1; end if; when zpxrmw2 => if (rdy_i = '1') then csm_next_state <= zpxrmw3; else csm_next_state <= zpxrmw2; end if; when zpxrmw3 => if (rdy_i = '1' and (zw_REG_OP = X"D6" or zw_REG_OP = X"F6")) then csm_next_state <= zpxrmw41; elsif (rdy_i = '1') then csm_next_state <= zpxrmw42; else csm_next_state <= zpxrmw3; end if; when zpxrmw41 => if (rdy_i = '1') then csm_next_state <= zpxrmw51; else csm_next_state <= zpxrmw41; end if; when zpxrmw51 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zpxrmw51; end if; when abrmw1 => if (rdy_i = '1') then csm_next_state <= abrmw2; else csm_next_state <= abrmw1; end if; when abrmw2 => if (rdy_i = '1') then csm_next_state <= abrmw3; else csm_next_state <= abrmw2; end if; when abrmw3 => if (rdy_i = '1' and (zw_REG_OP = X"CE" or zw_REG_OP = X"EE")) then csm_next_state <= abrmw41; elsif (rdy_i = '1') then csm_next_state <= abrmw42; else csm_next_state <= abrmw3; end if; when abrmw41 => if (rdy_i = '1') then csm_next_state <= abrmw51; else csm_next_state <= abrmw41; end if; when abrmw51 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= abrmw51; end if; when abxrmb1 => if (rdy_i = '1') then csm_next_state <= abxrmb2; else csm_next_state <= abxrmb1; end if; when abxrmb2 => if (rdy_i = '1') then csm_next_state <= abxrmb3; else csm_next_state <= abxrmb2; end if; when abxrmb3 => if (rdy_i = '1' AND zw_reg_0flag = '0' and (zw_REG_OP = X"DE" or zw_REG_OP = X"FE")) then csm_next_state <= abxrmb51; elsif (rdy_i = '1' and (zw_REG_OP = X"DE" or zw_REG_OP = X"FE")) then csm_next_state <= abxrmb41; elsif (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= abxrmb52; elsif (rdy_i = '1') then csm_next_state <= abxrmb42; else csm_next_state <= abxrmb3; end if; when abxrmb41 => if (rdy_i = '1') then csm_next_state <= abxrmb51; else csm_next_state <= abxrmb41; end if; when abxrmb51 => if (rdy_i = '1') then csm_next_state <= abxrmb61; else csm_next_state <= abxrmb51; end if; when abxrmb61 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= abxrmb61; end if; when zp2w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zp2w; end if; when zpx3w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zpx3w; end if; when zpy3w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zpy3w; end if; when ab3w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= ab3w; end if; when absx4w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= absx4w; end if; when absx3w => if (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= absx4w; else csm_next_state <= absx3w; end if; when absy4w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= absy4w; end if; when absy3w => if (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= absy4w; else csm_next_state <= absy3w; end if; when ind4w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= ind4w; end if; when indx5w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= indx5w; end if; when indy5w => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= indy5w; end if; when indy4w => if (rdy_i = '1' AND zw_reg_0flag = '0') then csm_next_state <= FETCH; elsif (rdy_i = '1') then csm_next_state <= indy5w; else csm_next_state <= indy4w; end if; when zprmw32 => if (rdy_i = '1') then csm_next_state <= zprmw41; else csm_next_state <= zprmw32; end if; when zpxrmw42 => if (rdy_i = '1') then csm_next_state <= zpxrmw51; else csm_next_state <= zpxrmw42; end if; when abrmw42 => if (rdy_i = '1') then csm_next_state <= abrmw51; else csm_next_state <= abrmw42; end if; when abxrmb52 => if (rdy_i = '1') then csm_next_state <= abxrmb61; else csm_next_state <= abxrmb52; end if; when abxrmb42 => if (rdy_i = '1') then csm_next_state <= abxrmb52; else csm_next_state <= abxrmb42; end if; when zp3 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zp3; end if; when zpx4 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= zpx4; end if; when ab4 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= ab4; end if; when ind5 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= ind5; end if; when indx6 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= indx6; end if; when imm2 => if (rdy_i = '1') then csm_next_state <= FETCH; else csm_next_state <= imm2; end if; when others => csm_next_state <= RES; end case; end process csm_nextstate_proc; ----------------------------------------------------------------- csm_output_proc : process ( adr_nxt_pc_i, adr_pc_i, adr_sp_i, csm_current_state, d_i, d_regs_out_i, irq_n_i, nmi_i, op_finished, q_x_i, q_y_i, rdy_i, reg_F, reg_op_finished, sel_pc_in, sel_pc_val, sel_sp_as, sel_sp_in, sig_D_OUT, sig_PC, sig_RD, sig_RWn, sig_WR, zw_REG_OP, zw_b1, zw_b11, zw_b12, zw_b2, zw_b3, zw_b4, zw_b5, zw_b6, zw_reg_0flag, zw_w3 ) ----------------------------------------------------------------- begin -- Default Assignment a_o <= sig_PC; adr_o <= X"0000"; ch_a_o <= X"00"; ch_b_o <= X"00"; d_o <= sig_D_OUT; ld_o <= "00"; ld_pc_o <= '0'; ld_sp_o <= '0'; offset_o <= X"0000"; rd_o <= sig_RD; rst_nmi_o <= '0'; sel_pc_in_o <= sel_pc_in; sel_pc_val_o <= sel_pc_val; sel_sp_as_o <= sel_sp_as; sel_sp_in_o <= sel_sp_in; wr_n_o <= sig_RWn; wr_o <= sig_WR; -- Default Assignment To Internals adc_sbc_finished <= '0'; irq_finished <= '0'; op_fetch <= '0'; op_finished <= '0'; op_finished_det <= reg_op_finished AND (op_finished XOR reg_op_finished); rmb_started <= '0'; rst_finished <= '0'; sel_pc_in <= '0'; sel_pc_val <= "00"; sel_sp_as <= '1'; sel_sp_in <= '0'; sig_D_OUT <= X"00"; sig_PC <= X"0000"; sig_RD <= '1'; sig_RWn <= '1'; sig_SYNC <= '0'; sig_WR <= '0'; -- Combined Actions case csm_current_state is when res2 => sig_PC <= adr_pc_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when res4 => sig_PC <= adr_sp_i; adr_o <= X"FFFB"; sel_pc_in <= '1'; sel_pc_val <= "00"; ld_pc_o <= '1'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when res5 => sig_PC <= adr_sp_i; when res6 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when res7 => sig_PC <= adr_pc_i; adr_o <= d_i & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; rst_finished <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when res3 => sig_PC <= adr_sp_i; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when RES => sig_PC <= adr_pc_i; sig_SYNC <= '1'; when FETCH => sig_PC <= adr_pc_i; op_fetch <= '1'; sig_RWn <= '1'; sig_RD <= '1'; sig_SYNC <= NOT (rdy_i); ld_pc_o <= '1'; if ((d_i = X"00") and (rdy_i = '1')) then ld_o <= "11"; elsif ((nmi_i = '1') and (rdy_i = '1')) then ld_o <= "11"; elsif ((irq_n_i = '0' and reg_F(2) = '0') and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"8F" or d_i = X"9F" or d_i = X"AF" or d_i = X"BF" or d_i = X"CF" or d_i = X"DF" or d_i = X"EF" or d_i = X"FF" or d_i = X"0F" or d_i = X"1F" or d_i = X"2F" or d_i = X"3F" or d_i = X"4F" or d_i = X"5F" or d_i = X"6F" or d_i = X"7F") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"90" or d_i = X"B0" or d_i = X"F0" or d_i = X"30" or d_i = X"D0" or d_i = X"10" or d_i = X"50" or d_i = X"70" or d_i = X"80") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"4C" or d_i = X"6C" or d_i = X"7C") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"20") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"68") and (rdy_i = '1')) then elsif ((d_i = X"FA") and (rdy_i = '1')) then elsif ((d_i = X"C6" or d_i = X"E6" or d_i = X"66" or d_i = X"06" or d_i = X"46" or d_i = X"26" or d_i (3 downto 0) = X"7" or d_i = X"14" or d_i = X"04") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"D6" or d_i = X"F6" or d_i = X"76" or d_i = X"16" or d_i = X"56" or d_i = X"36") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"CE" or d_i = X"EE" or d_i = X"6E" or d_i = X"0E" or d_i = X"4E" or d_i = X"2E" or d_i = X"1C" or d_i = X"0C") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"DE" or d_i = X"FE" or d_i = X"7E" or d_i = X"1E" or d_i = X"5E" or d_i = X"3E") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"09" or d_i = X"29" or d_i = X"49" or d_i = X"69" or d_i = X"89" or d_i = X"A0" or d_i = X"A2" or d_i = X"A9" or d_i = X"C9" or d_i = X"E0" or d_i = X"C0" or d_i = X"E9") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"05" or d_i = X"25" or d_i = X"45" or d_i = X"65" or d_i = X"A5" or d_i = X"24" or d_i = X"C5" or d_i = X"E4" or d_i = X"C4" or d_i = X"A6" or d_i = X"A4" or d_i = X"E5" or d_i = X"85" or d_i = X"86" or d_i = X"84" or d_i = X"64") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"15" or d_i = X"35" or d_i = X"55" or d_i = X"75" or d_i = X"B5" or d_i = X"34" or d_i = X"D5" or d_i = X"B4" or d_i = X"F5" or d_i = X"95" or d_i = X"94" or d_i = X"74") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"B6" or d_i = X"96") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"6D" or d_i = X"2D" or d_i = X"2C" or d_i = X"CD" or d_i = X"CC" or d_i = X"EC" or d_i = X"4D" or d_i = X"AD" or d_i = X"AE" or d_i = X"AC" or d_i = X"0D" or d_i = X"ED" or d_i = X"8D" or d_i = X"8E" or d_i = X"8C" or d_i = X"9C") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"7D" or d_i = X"3D" or d_i = X"3C" or d_i = X"DD" or d_i = X"5D" or d_i = X"BD" or d_i = X"BC" or d_i = X"1D" or d_i = X"FD" or d_i = X"9D" or d_i = X"9E") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"79" or d_i = X"39" or d_i = X"D9" or d_i = X"5D" or d_i = X"59" or d_i = X"B9" or d_i = X"BE" or d_i = X"19" or d_i = X"F9" or d_i = X"99") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"72" or d_i = X"32" or d_i = X"D2" or d_i = X"59" or d_i = X"52" or d_i = X"B2" or d_i = X"12" or d_i = X"F2" or d_i = X"92") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"71" or d_i = X"31" or d_i = X"D1" or d_i = X"51" or d_i = X"B1" or d_i = X"11" or d_i = X"F1" or d_i = X"91") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"61" or d_i = X"21" or d_i = X"C1" or d_i = X"41" or d_i = X"A1" or d_i = X"01" or d_i = X"E1" or d_i = X"81") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"B8" or d_i = X"38" or d_i = X"18" or d_i = X"F8" or d_i = X"D8" or d_i = X"78" or d_i = X"58" or d_i = X"0A" or d_i = X"4A" or d_i = X"2A" or d_i = X"6A" or d_i = X"A8" or d_i = X"98" or d_i = X"BA" or d_i = X"8A" or d_i = X"AA" or d_i = X"C8" or d_i = X"E8" or d_i = X"1A" or d_i = X"88" or d_i = X"CA" or d_i = X"3A") and (rdy_i = '1')) then elsif ((d_i = X"7A") and (rdy_i = '1')) then elsif ((d_i = X"28") and (rdy_i = '1')) then elsif ((d_i = X"9A") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"60") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"40") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"08") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"5A") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"DA") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"48") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"EA") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i(3 downto 0) = X"3" or d_i(3 downto 0) = X"B") and (rdy_i = '1')) then ld_o <= "11"; sig_SYNC <= '1'; elsif ((d_i = X"02" or d_i = X"22" or d_i = X"42" or d_i = X"62" or d_i = X"82" or d_i = X"C2" or d_i = X"E2") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"44") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"54" or d_i = X"D4" or d_i = X"F4") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"DC" or d_i = X"FC") and (rdy_i = '1')) then ld_o <= "11"; elsif ((d_i = X"5C") and (rdy_i = '1')) then ld_o <= "11"; end if; when nop1 => sig_PC <= adr_pc_i; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when txs1 => sig_PC <= adr_pc_i; sel_sp_in <= '1'; sel_sp_as <= '0'; ld_sp_o <= '1'; if (rdy_i = '1') then adr_o <= X"01" & q_x_i; ld_o <= "11"; sig_SYNC <= '1'; end if; when bxx1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1' and ( (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when bxx2 => sig_PC <= adr_pc_i; sel_pc_in <= '0'; sel_pc_val <= "10"; offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_pc_o <= '1'; if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when bxx3 => sig_PC <= zw_b3 & adr_pc_i (7 downto 0); if (rdy_i = '1') then sig_SYNC <= '1'; end if; when jmp1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"4C") then ld_o <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"6C") then ld_o <= "11"; elsif (rdy_i = '1' and zw_REG_OP = X"7C") then ld_o <= "11"; end if; when jmp2_1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when jmp4_12 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when jmp_ex => sig_PC <= adr_pc_i; adr_o <= d_i & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when jmp2_2 => sig_PC <= adr_pc_i; when jmp3_1 => sig_PC <= zw_b6 & zw_b5; adr_o <= zw_b6 & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when jsr1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when jsr2 => sig_PC <= adr_sp_i; when jsr3 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when jsr4 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b12; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when jsr5 => sig_PC <= adr_pc_i; adr_o <= d_i & zw_b1; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when brk1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when brk2 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when brk3 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b12; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when brk4 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; ld_sp_o <= '1'; irq_finished <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when brk6 => sig_PC <= X"FFFF"; adr_o <= d_i & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when brk5 => sig_PC <= X"FFFE"; when rti1 => sig_PC <= adr_pc_i; when rti2 => sig_PC <= adr_sp_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when rti3 => sig_PC <= adr_sp_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_sp_o <= '1'; op_finished <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when rti4 => sig_PC <= adr_sp_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when rti5 => sig_PC <= adr_sp_i; adr_o <= d_i & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when rts1 => sig_PC <= adr_pc_i; when rts2 => sig_PC <= adr_sp_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when rts3 => sig_PC <= adr_sp_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when rts4 => sig_PC <= adr_sp_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when rts5 => sig_PC <= zw_b6 & zw_b5; adr_o <= zw_b6 & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "00"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when pha1 => sig_PC <= adr_pc_i; when pha2 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= d_regs_out_i; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when php1 => sig_PC <= adr_pc_i; when php2 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= reg_F OR X"30"; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when pla1 => sig_PC <= adr_pc_i; when pla2 => sig_PC <= adr_pc_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_pc_o <= '1'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when pla3 => sig_PC <= adr_sp_i; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when plp1 => sig_PC <= adr_pc_i; when plp2 => sig_PC <= adr_pc_i; sel_sp_in <= '0'; sel_sp_as <= '0'; ld_pc_o <= '1'; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when plp3 => sig_PC <= adr_sp_i; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when irq1 => sig_PC <= adr_pc_i; when irq2 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when irq3 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b12; ld_sp_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when irq5b => sig_PC <= X"FFFE"; when irq5a => sig_PC <= X"FFFA"; when irq4 => sig_PC <= adr_sp_i; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; ld_sp_o <= '1'; irq_finished <= '1'; if (rdy_i = '1' and nmi_i = '1') then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when irq6a => sig_PC <= X"FFFB"; adr_o <= d_i & zw_b5; rst_nmi_o <= '1'; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when nop22 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when nop231 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when nop232 => sig_PC <= adr_pc_i; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when nop241 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when nop242 => sig_PC <= adr_pc_i; when nop243 => sig_PC <= adr_pc_i; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when nop341 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when nop342 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when nop343 => sig_PC <= adr_pc_i; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when nop381 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when nop382 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when nop383 => sig_PC <= adr_pc_i; when nop384 => sig_PC <= adr_pc_i; when nop387 => sig_PC <= adr_pc_i; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when nop385 => sig_PC <= adr_pc_i; when nop386 => sig_PC <= adr_pc_i; when jmp3_2 => sig_PC <= zw_b6 & zw_b5; adr_o <= zw_b6 & zw_b5; offset_o <= (X"00" & q_x_i); sel_pc_in <= '1'; sel_pc_val <= "10"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when bbr1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when bbr5 => sig_PC <= zw_w3; sel_pc_in <= '0'; sel_pc_val <= "10"; offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); ld_pc_o <= '1'; if (rdy_i = '1' and zw_b3 = adr_nxt_pc_i (15 downto 8)) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when bbr4 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1' and ( (zw_b1(0) = '0' and zw_REG_OP = X"8F") or (zw_b1(1) = '0' and zw_REG_OP = X"9F") or (zw_b1(2) = '0' and zw_REG_OP = X"AF") or (zw_b1(3) = '0' and zw_REG_OP = X"BF") or (zw_b1(4) = '0' and zw_REG_OP = X"CF") or (zw_b1(5) = '0' and zw_REG_OP = X"DF") or (zw_b1(6) = '0' and zw_REG_OP = X"EF") or (zw_b1(7) = '0' and zw_REG_OP = X"FF") or (zw_b1(0) = '1' and zw_REG_OP = X"0F") or (zw_b1(1) = '1' and zw_REG_OP = X"1F") or (zw_b1(2) = '1' and zw_REG_OP = X"2F") or (zw_b1(3) = '1' and zw_REG_OP = X"3F") or (zw_b1(4) = '1' and zw_REG_OP = X"4F") or (zw_b1(5) = '1' and zw_REG_OP = X"5F") or (zw_b1(6) = '1' and zw_REG_OP = X"6F") or (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then ld_o <= "11"; sig_SYNC <= '1'; elsif (rdy_i = '1') then ld_o <= "11"; end if; when bbr2 => sig_PC <= X"00" & zw_b2; when bbr3 => sig_PC <= X"00" & zw_b2; when bbr6 => sig_PC <= zw_b3 & adr_pc_i (7 downto 0); if (rdy_i = '1') then sig_SYNC <= '1'; end if; when RES0 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when zp1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1' and (zw_REG_OP = X"85" OR zw_REG_OP = X"86" OR zw_REG_OP = X"64" OR zw_REG_OP = X"84")) then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when zp2 => sig_PC <= X"00" & zw_b5; op_finished <= '1'; if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"65" OR zw_REG_OP = X"E5")) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when zpx1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; when zpx2 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b5; ch_b_o <= q_x_i; ld_pc_o <= '1'; if (rdy_i = '1' and (zw_REG_OP = X"95" OR zw_REG_OP = X"74" OR zw_REG_OP = X"94")) then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when zpx3 => sig_PC <= X"00" & zw_b1; op_finished <= '1'; if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"75" OR zw_REG_OP = X"F5")) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when ab1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when ab2 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1' and (zw_REG_OP = X"8D" OR zw_REG_OP = X"8E" OR zw_REG_OP = X"9C" OR zw_REG_OP = X"8C")) then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when ab3 => sig_PC <= zw_b6 & zw_b5; op_finished <= '1'; if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"6D" OR zw_REG_OP = X"ED")) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when absx1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when absx2 => sig_PC <= adr_pc_i; ch_a_o <= zw_b5; ch_b_o <= q_x_i; ld_pc_o <= '1'; if (rdy_i = '1' and (zw_REG_OP = X"9D" OR zw_REG_OP = X"9E")) then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when absx4 => sig_PC <= zw_b3 & zw_b1; op_finished <= '1'; adc_sbc_finished <= reg_F(3); if ((rdy_i = '1') and ((zw_REG_OP = X"7D" or zw_REG_OP = X"FD") and reg_F(3) = '1')) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when absx3 => sig_PC <= zw_b6 & zw_b1; ch_a_o <= zw_b6; ch_b_o <= "0000000" & zw_reg_0flag; op_finished <= NOT(zw_reg_0flag); if ((rdy_i = '1' AND zw_reg_0flag = '0') and ((zw_REG_OP = X"7D" or zw_REG_OP = X"FD") and reg_F(3) = '1')) then elsif (rdy_i = '1' AND zw_reg_0flag = '0') then sig_SYNC <= '1'; end if; when ind1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; when ind3 => sig_PC <= X"00" & zw_b1; ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"92") then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when ind4 => sig_PC <= zw_b5 & zw_b6; op_finished <= '1'; if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"72" OR zw_REG_OP = X"F2")) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when ind2 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b5; ch_b_o <= X"01"; when indy1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; when indy2 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b5; ch_b_o <= X"01"; when indy3 => sig_PC <= X"00" & zw_b1; ch_a_o <= zw_b2; ch_b_o <= q_y_i; ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"91") then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when indy5 => sig_PC <= zw_b3 & zw_b6; op_finished <= '1'; adc_sbc_finished <= reg_F(3); if ((rdy_i = '1') and ((zw_REG_OP = X"71" or zw_REG_OP = X"F1") and reg_F(3) = '1')) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when indy4 => sig_PC <= zw_b5 & zw_b6; ch_a_o <= zw_b5; ch_b_o <= "0000000" & zw_reg_0flag; op_finished <= NOT(zw_reg_0flag); if ((rdy_i = '1' AND zw_reg_0flag = '0') and ((zw_REG_OP = X"71" or zw_REG_OP = X"F1") and reg_F(3) = '1')) then elsif (rdy_i = '1' AND zw_reg_0flag = '0') then sig_SYNC <= '1'; end if; when indx1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; when indx4 => sig_PC <= X"00" & zw_b6; ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"81") then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when indx2 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b5; ch_b_o <= q_x_i; when indx3 => sig_PC <= X"00" & zw_b1; ch_a_o <= zw_b1; ch_b_o <= X"01"; when indx5 => sig_PC <= zw_b2 & zw_b5; op_finished <= '1'; if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"61" OR zw_REG_OP = X"E1")) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when zpy1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; when zpy2 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b5; ch_b_o <= q_y_i; ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"96") then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when zpy3 => sig_PC <= X"00" & zw_b1; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when absy2 => sig_PC <= adr_pc_i; ch_a_o <= zw_b5; ch_b_o <= q_y_i; ld_pc_o <= '1'; if (rdy_i = '1' and zw_REG_OP = X"99") then ld_o <= "11"; elsif (rdy_i = '1') then ld_o <= "11"; end if; when absy1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when absy4 => sig_PC <= zw_b3 & zw_b1; op_finished <= '1'; adc_sbc_finished <= reg_F(3); if ((rdy_i = '1') and ((zw_REG_OP = X"79" or zw_REG_OP = X"F9") and reg_F(3) = '1')) then elsif (rdy_i = '1') then sig_SYNC <= '1'; end if; when absy3 => sig_PC <= zw_b6 & zw_b1; ch_a_o <= zw_b6; ch_b_o <= "0000000" & zw_reg_0flag; op_finished <= NOT(zw_reg_0flag); if ((rdy_i = '1' AND zw_reg_0flag = '0') and ((zw_REG_OP = X"79" or zw_REG_OP = X"F9") and reg_F(3) = '1')) then elsif (rdy_i = '1' AND zw_reg_0flag = '0') then sig_SYNC <= '1'; end if; when imm1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; op_finished <= '1'; if (rdy_i = '1' and reg_F(3) = '1' and (zw_REG_OP = X"69" OR zw_REG_OP = X"E9")) then elsif (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when imp1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; op_finished <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when irq6b => sig_PC <= X"FFFF"; adr_o <= d_i & zw_b5; sel_pc_in <= '1'; sel_pc_val <= "11"; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when absx5 => sig_PC <= zw_b3 & zw_b1; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when absy5 => sig_PC <= zw_b3 & zw_b1; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when indy6 => sig_PC <= zw_b3 & zw_b6; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when zprmw1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when zprmw2 => sig_PC <= X"00" & zw_b5; rmb_started <= '1'; when zprmw31 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b2; ch_b_o <= zw_b4; when zprmw41 => sig_PC <= X"00" & zw_b5; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when zpxrmw1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; when zpxrmw2 => sig_PC <= X"00" & zw_b5; ch_a_o <= zw_b5; ch_b_o <= q_x_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when zpxrmw3 => sig_PC <= X"00" & zw_b1; rmb_started <= '1'; when zpxrmw41 => sig_PC <= X"00" & zw_b1; ch_a_o <= zw_b2; ch_b_o <= zw_b4; when zpxrmw51 => sig_PC <= X"00" & zw_b1; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when abrmw1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when abrmw2 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when abrmw3 => sig_PC <= zw_b6 & zw_b5; rmb_started <= '1'; when abrmw41 => sig_PC <= zw_b6 & zw_b5; ch_a_o <= zw_b2; ch_b_o <= zw_b4; when abrmw51 => sig_PC <= zw_b6 & zw_b5; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when abxrmb1 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when abxrmb2 => sig_PC <= adr_pc_i; ch_a_o <= zw_b5; ch_b_o <= q_x_i; ld_pc_o <= '1'; if (rdy_i = '1') then ld_o <= "11"; end if; when abxrmb3 => sig_PC <= zw_b6 & zw_b1; rmb_started <= NOT(zw_reg_0flag); ch_a_o <= zw_b6; ch_b_o <= "0000000" & zw_reg_0flag; when abxrmb41 => sig_PC <= zw_b3 & zw_b1; when abxrmb51 => sig_PC <= zw_b3 & zw_b1; ch_a_o <= zw_b2; ch_b_o <= zw_b4; when abxrmb61 => sig_PC <= zw_b3 & zw_b1; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when zp2w => sig_PC <= X"00" & zw_b5; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when zpx3w => sig_PC <= X"00" & zw_b1; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when zpy3w => sig_PC <= X"00" & zw_b1; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when ab3w => sig_PC <= zw_b6 & zw_b5; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when absx4w => sig_PC <= zw_b3 & zw_b1; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when absx3w => sig_PC <= zw_b6 & zw_b1; ch_a_o <= zw_b6; ch_b_o <= "0000000" & zw_reg_0flag; sig_RWn <= zw_reg_0flag; sig_RD <= zw_reg_0flag; sig_WR <= NOT(zw_reg_0flag); sig_D_OUT <= zw_b11; op_finished <= NOT(zw_reg_0flag); if (rdy_i = '1' AND zw_reg_0flag = '0') then sig_SYNC <= '1'; end if; when absy4w => sig_PC <= zw_b3 & zw_b1; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when absy3w => sig_PC <= zw_b6 & zw_b1; ch_a_o <= zw_b6; ch_b_o <= "0000000" & zw_reg_0flag; sig_RWn <= zw_reg_0flag; sig_RD <= zw_reg_0flag; sig_WR <= NOT(zw_reg_0flag); sig_D_OUT <= zw_b11; op_finished <= NOT(zw_reg_0flag); if (rdy_i = '1' AND zw_reg_0flag = '0') then sig_SYNC <= '1'; end if; when ind4w => sig_PC <= zw_b5 & zw_b6; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when indx5w => sig_PC <= zw_b2 & zw_b5; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when indy5w => sig_PC <= zw_b3 & zw_b6; sig_RWn <= '0'; sig_RD <= '0'; sig_WR <= '1'; sig_D_OUT <= zw_b11; op_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when indy4w => sig_PC <= zw_b5 & zw_b6; ch_a_o <= zw_b5; ch_b_o <= "0000000" & zw_reg_0flag; sig_RWn <= zw_reg_0flag; sig_RD <= zw_reg_0flag; sig_WR <= NOT(zw_reg_0flag); sig_D_OUT <= zw_b11; op_finished <= NOT(zw_reg_0flag); if (rdy_i = '1' AND zw_reg_0flag = '0') then sig_SYNC <= '1'; end if; when zprmw32 => sig_PC <= X"00" & zw_b5; ch_a_o <= "00000" & zw_REG_OP (6 downto 4); rmb_started <= '1'; when zpxrmw42 => sig_PC <= X"00" & zw_b1; rmb_started <= '1'; when abrmw42 => sig_PC <= zw_b6 & zw_b5; rmb_started <= '1'; when abxrmb52 => sig_PC <= zw_b3 & zw_b1; rmb_started <= '1'; when abxrmb42 => sig_PC <= zw_b3 & zw_b1; rmb_started <= '1'; when zp3 => sig_PC <= X"00" & zw_b5; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when zpx4 => sig_PC <= X"00" & zw_b1; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when ab4 => sig_PC <= zw_b6 & zw_b5; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when ind5 => sig_PC <= zw_b5 & zw_b6; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when indx6 => sig_PC <= zw_b2 & zw_b5; adc_sbc_finished <= '1'; if (rdy_i = '1') then sig_SYNC <= '1'; end if; when imm2 => sig_PC <= adr_pc_i; ld_pc_o <= '1'; adc_sbc_finished <= '1'; if (rdy_i = '1') then ld_o <= "11"; sig_SYNC <= '1'; end if; when others => null; end case; end process csm_output_proc; ----------------------------------------------------------------- csm_functions_clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then csm_functions_current_state <= f_rst; -- Default Reset Values d_regs_out_bak_i <= (others => '0'); q_a_bak_i <= (others => '0'); q_x_bak_i <= (others => '0'); q_y_bak_i <= (others => '0'); reg_F <= "00110100"; reg_F_bak <= (others => '0'); zw_b10 <= "00" & X"00"; zw_b14 <= X"00"; zw_b7 <= "00" & X"00"; zw_b8 <= "00" & X"00"; zw_b9 <= "00" & X"00"; zw_din <= X"00"; elsif (clk_clk_i'event and clk_clk_i = '1') then csm_functions_current_state <= csm_functions_next_state; -- Default Assignment To Internals d_regs_out_bak_i <= d_regs_out_bak_i; q_a_bak_i <= q_a_bak_i; q_x_bak_i <= q_x_bak_i; q_y_bak_i <= q_y_bak_i; reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); reg_F_bak <= reg_F_bak; zw_b10 <= zw_b10; zw_b14 <= zw_b14; zw_b7 <= zw_b7; zw_b8 <= zw_b8; zw_b9 <= zw_b9; zw_din <= zw_din; -- Combined Actions case csm_functions_current_state is when f_idle => zw_din <= d_i; q_a_bak_i <= q_a_i; q_x_bak_i <= q_x_i; q_y_bak_i <= q_y_i; reg_F_bak <= reg_F; d_regs_out_bak_i <= d_regs_out_i; when f_and => zw_din <= d_i; reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_lda => zw_din <= d_i; reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_eor => zw_din <= d_i; reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_cmp => zw_din <= d_i; reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= c_detect_out; when f_ora => zw_din <= d_i; reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_clc => reg_F(0) <= '0'; when f_sec => reg_F(0) <= '1'; when f_cld => reg_F(3) <= '0'; when f_sed => reg_F(3) <= '1'; when f_clv => reg_F(6) <= '0'; when f_cli => reg_F(2) <= '0'; when f_sei => reg_F(2) <= '1'; when f_rti => zw_din <= d_i; reg_F(7 downto 6) <= zw_din(7 downto 6); reg_F(3 downto 0) <= zw_din(3 downto 0); when f_irq => reg_F(2) <= '1'; reg_F(3) <= '0'; when f_res => reg_F(2) <= '1'; reg_F(3) <= '0'; reg_F(5) <= '1'; when f_bit1 => zw_din <= d_i; reg_F(1) <= z_detect_out; when f_bit2 => zw_din <= d_i; reg_F(7) <= zw_din(7); reg_F(6) <= zw_din(6); reg_F(1) <= z_detect_out; when f_de_in_a => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_adc_bin => zw_din <= d_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_bak_i(7)) AND (NOT zw_din(7))) OR (NOT zw_ALU(7) AND (q_a_bak_i(7)) AND (zw_din(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= zw_ALU(8); when f_sbc_bin => zw_din <= d_i; reg_F(7) <= zw_ALU(7); reg_F(6) <= (zw_ALU(7) AND (NOT q_a_bak_i(7)) AND (zw_din(7))) OR (NOT zw_ALU(7) AND (q_a_bak_i(7)) AND (NOT zw_din(7))); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); reg_F(0) <= (zw_ALU(8) AND (NOT q_a_bak_i(7)) AND (NOT zw_din(7))) OR (zw_ALU(8) AND (q_a_bak_i(7)) AND (zw_din(7))) OR (NOT zw_ALU(8) AND (q_a_bak_i(7)) AND (NOT zw_din(7))) OR (zw_ALU(8) AND (q_a_bak_i(7)) AND (NOT zw_din(7))); when f_adc_dec => zw_din <= d_i; reg_F(6) <= (zw_ALU5(3) XOR q_a_bak_i(7)) AND (NOT (q_a_bak_i(7) XOR zw_din(7))); reg_F(0) <= zw_ALU4(4); zw_b8(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; zw_b10(4 downto 0) <= unsigned ('0' & q_a_bak_i(7 downto 4)) + unsigned ('0' & zw_din(7 downto 4)) + (zw_ALU3(4)); zw_b7(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; zw_b9(4 downto 0) <= unsigned ('0' & q_a_bak_i(3 downto 0)) + unsigned ('0' & zw_din(3 downto 0)) + reg_F_bak(0); when f_adc_dec1 => reg_F(7) <= zw_ALU(7); reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR zw_ALU(0)); when f_sbc_dec => zw_din <= d_i; reg_F(6) <= (zw_ALU2(3) XOR q_a_bak_i(7)) AND (q_a_bak_i(7) XOR zw_din(7)); reg_F(0) <= (zw_ALU2(4)); zw_b9(7 downto 0) <= '0' & (NOT zw_ALU2(4)) & (NOT zw_ALU2(4)) & '0' & '0' & (NOT zw_ALU1(4)) & (NOT zw_ALU1(4)) & '0'; zw_b8(5 downto 0) <= unsigned ("00" & q_a_bak_i(7 downto 4)) + unsigned ("00" & NOT (zw_din(7 downto 4))) + (zw_ALU1(4)); zw_b7(5 downto 0) <= unsigned ("00" & q_a_bak_i(3 downto 0)) + unsigned ("00" & NOT (zw_din(3 downto 0))) + reg_F_bak(0); when f_sbc_dec1 => reg_F(7) <= zw_ALU(7); reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR (zw_ALU(0))); when f_asla => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_l_c_out; when f_lsra => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_r_c_out; when f_rola => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_l_c_out; when f_rora => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_r_c_out; when f_tax => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_tsx => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_decr => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; when f_asl => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_l_c_out; when f_lsr => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_r_c_out; when f_rol => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_l_c_out; when f_ror => reg_F(7) <= n_detect_out; reg_F(1) <= z_detect_out; reg_F(0) <= shift_rot_r_c_out; when f_trb => reg_F(1) <= z_detect_out; when f_tsb => reg_F(1) <= z_detect_out; when others => null; end case; end if; end process csm_functions_clocked_proc; ----------------------------------------------------------------- csm_functions_nextstate_proc : process ( adc_sbc_finished, csm_functions_current_state, irq_finished, op_finished, op_finished_det, reg_F, rmb_started, rst_finished, zw_REG_OP ) ----------------------------------------------------------------- begin case csm_functions_current_state is when f_idle => if (op_finished = '1' and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or zw_REG_OP = X"35" or zw_REG_OP = X"2D" or zw_REG_OP = X"3D" or zw_REG_OP = X"39" or zw_REG_OP = X"21" or zw_REG_OP = X"31" or zw_REG_OP = X"32")) then csm_functions_next_state <= f_and; elsif (op_finished = '1' and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then csm_functions_next_state <= f_cmp; elsif (op_finished = '1' and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or zw_REG_OP = X"52")) then csm_functions_next_state <= f_eor; elsif (op_finished = '1' and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or zw_REG_OP = X"12")) then csm_functions_next_state <= f_ora; elsif (op_finished = '1' and (zw_REG_OP = X"A9" or zw_REG_OP = X"A5" or zw_REG_OP = X"B5" or zw_REG_OP = X"AD" or zw_REG_OP = X"BD" or zw_REG_OP = X"B9" or zw_REG_OP = X"A1" or zw_REG_OP = X"B1" or zw_REG_OP = X"B2" or zw_REG_OP = X"A2" or zw_REG_OP = X"A6" or zw_REG_OP = X"B6" or zw_REG_OP = X"AE" or zw_REG_OP = X"BE" or zw_REG_OP = X"A0" or zw_REG_OP = X"A4" or zw_REG_OP = X"B4" or zw_REG_OP = X"AC" or zw_REG_OP = X"BC" or zw_REG_OP = X"68" or zw_REG_OP = X"FA" or zw_REG_OP = X"7A")) then csm_functions_next_state <= f_lda; elsif (op_finished = '1' and zw_REG_OP = X"18") then csm_functions_next_state <= f_clc; elsif (op_finished = '1' and zw_REG_OP = X"38") then csm_functions_next_state <= f_sec; elsif (op_finished = '1' and zw_REG_OP = X"D8") then csm_functions_next_state <= f_cld; elsif (op_finished = '1' and zw_REG_OP = X"F8") then csm_functions_next_state <= f_sed; elsif (op_finished = '1' and zw_REG_OP = X"B8") then csm_functions_next_state <= f_clv; elsif (op_finished = '1' and zw_REG_OP = X"58") then csm_functions_next_state <= f_cli; elsif (op_finished = '1' and (zw_REG_OP = X"78")) then csm_functions_next_state <= f_sei; elsif (op_finished = '1' and (zw_REG_OP = X"40" or zw_REG_OP = X"28")) then csm_functions_next_state <= f_rti; elsif (irq_finished = '1') then csm_functions_next_state <= f_irq; elsif (rst_finished = '1') then csm_functions_next_state <= f_res; elsif (op_finished = '1' and zw_REG_OP = X"89") then csm_functions_next_state <= f_bit1; elsif (op_finished = '1' and (zw_REG_OP = X"24" or zw_REG_OP = X"34" or zw_REG_OP = X"2C" or zw_REG_OP = X"3C")) then csm_functions_next_state <= f_bit2; elsif (op_finished = '1' and (zw_REG_OP = X"3A" or zw_REG_OP = X"CA" or zw_REG_OP = X"88" or zw_REG_OP = X"1A" or zw_REG_OP = X"E8" or zw_REG_OP = X"C8")) then csm_functions_next_state <= f_de_in_a; elsif (op_finished = '1' and reg_F(3) = '0' and (zw_REG_OP = X"69" or zw_REG_OP = X"65" or zw_REG_OP = X"75" or zw_REG_OP = X"6D" or zw_REG_OP = X"72" or zw_REG_OP = X"7D" or zw_REG_OP = X"79" or zw_REG_OP = X"71" or zw_REG_OP = X"61")) then csm_functions_next_state <= f_adc_bin; elsif (op_finished = '1' and reg_F(3) = '0' and (zw_REG_OP = X"E9" or zw_REG_OP = X"E5" or zw_REG_OP = X"F5" or zw_REG_OP = X"ED" or zw_REG_OP = X"F2" or zw_REG_OP = X"FD" or zw_REG_OP = X"F9" or zw_REG_OP = X"F1" or zw_REG_OP = X"E1")) then csm_functions_next_state <= f_sbc_bin; elsif (op_finished = '1' and reg_F(3) = '1' and (zw_REG_OP = X"69" or zw_REG_OP = X"65" or zw_REG_OP = X"75" or zw_REG_OP = X"6D" or zw_REG_OP = X"72" or zw_REG_OP = X"7D" or zw_REG_OP = X"79" or zw_REG_OP = X"71" or zw_REG_OP = X"61")) then csm_functions_next_state <= f_adc_dec; elsif (op_finished = '1' and reg_F(3) = '1' and (zw_REG_OP = X"E9" or zw_REG_OP = X"E5" or zw_REG_OP = X"F5" or zw_REG_OP = X"ED" or zw_REG_OP = X"F2" or zw_REG_OP = X"FD" or zw_REG_OP = X"F9" or zw_REG_OP = X"F1" or zw_REG_OP = X"E1")) then csm_functions_next_state <= f_sbc_dec; elsif (op_finished = '1' and zw_REG_OP = X"0A") then csm_functions_next_state <= f_asla; elsif (op_finished = '1' and zw_REG_OP = X"4A") then csm_functions_next_state <= f_lsra; elsif (op_finished = '1' and zw_REG_OP = X"2A") then csm_functions_next_state <= f_rola; elsif (op_finished = '1' and zw_REG_OP = X"6A") then csm_functions_next_state <= f_rora; elsif (op_finished = '1' and (zw_REG_OP = X"AA" or zw_REG_OP = X"8A" or zw_REG_OP = X"A8" or zw_REG_OP = X"98")) then csm_functions_next_state <= f_tax; elsif (op_finished = '1' and zw_REG_OP = X"BA") then csm_functions_next_state <= f_tsx; elsif (op_finished = '1' and (zw_REG_OP = X"C6" or zw_REG_OP = X"E6" or zw_REG_OP = X"D6" or zw_REG_OP = X"F6" or zw_REG_OP = X"CE" or zw_REG_OP = X"EE" or zw_REG_OP = X"DE" or zw_REG_OP = X"FE")) then csm_functions_next_state <= f_decr; elsif (rmb_started = '1' and (zw_REG_OP = X"66" or zw_REG_OP = X"76" or zw_REG_OP = X"6E" or zw_REG_OP = X"7E")) then csm_functions_next_state <= f_ror; elsif (rmb_started = '1' and (zw_REG_OP = X"06" or zw_REG_OP = X"16" or zw_REG_OP = X"0E" or zw_REG_OP = X"1E")) then csm_functions_next_state <= f_asl; elsif (rmb_started = '1' and (zw_REG_OP = X"46" or zw_REG_OP = X"56" or zw_REG_OP = X"4E" or zw_REG_OP = X"5E")) then csm_functions_next_state <= f_lsr; elsif (rmb_started = '1' and (zw_REG_OP = X"26" or zw_REG_OP = X"36" or zw_REG_OP = X"2E" or zw_REG_OP = X"3E")) then csm_functions_next_state <= f_rol; elsif (rmb_started = '1' and zw_REG_OP (7) = '0' and zw_REG_OP (3 downto 0) = X"7") then csm_functions_next_state <= f_rmb; elsif (rmb_started = '1' and zw_REG_OP (7) = '1' and zw_REG_OP (3 downto 0) = X"7") then csm_functions_next_state <= f_smb; elsif (rmb_started = '1' and (zw_REG_OP = X"14" or zw_REG_OP = X"1C")) then csm_functions_next_state <= f_trb; elsif (rmb_started = '1' and (zw_REG_OP = X"04" or zw_REG_OP = X"0C")) then csm_functions_next_state <= f_tsb; else csm_functions_next_state <= f_idle; end if; when f_and => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_and; end if; when f_lda => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_lda; end if; when f_rst => csm_functions_next_state <= f_idle; when f_eor => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_eor; end if; when f_cmp => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_cmp; end if; when f_ora => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_ora; end if; when f_clc => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_clc; end if; when f_sec => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_sec; end if; when f_cld => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_cld; end if; when f_sed => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_sed; end if; when f_clv => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_clv; end if; when f_cli => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_cli; end if; when f_sei => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_sei; end if; when f_rti => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_rti; end if; when f_irq => if (irq_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_irq; end if; when f_res => if (rst_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_res; end if; when f_bit1 => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_bit1; end if; when f_bit2 => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_bit2; end if; when f_de_in_a => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_de_in_a; end if; when f_adc_bin => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_adc_bin; end if; when f_sbc_bin => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_sbc_bin; end if; when f_adc_dec => if (op_finished_det = '1') then csm_functions_next_state <= f_adc_dec1; else csm_functions_next_state <= f_adc_dec; end if; when f_adc_dec1 => if (adc_sbc_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_adc_dec1; end if; when f_sbc_dec => if (op_finished_det = '1') then csm_functions_next_state <= f_sbc_dec1; else csm_functions_next_state <= f_sbc_dec; end if; when f_sbc_dec1 => if (adc_sbc_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_sbc_dec1; end if; when f_asla => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_asla; end if; when f_lsra => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_lsra; end if; when f_rola => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_rola; end if; when f_rora => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_rora; end if; when f_tax => if (op_finished_det = '1') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_tax; end if; when f_tsx => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_tsx; end if; when f_decr => if (op_finished = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_decr; end if; when f_asl => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_asl; end if; when f_lsr => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_lsr; end if; when f_rol => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_rol; end if; when f_ror => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_ror; end if; when f_rmb => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_rmb; end if; when f_smb => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_smb; end if; when f_trb => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_trb; end if; when f_tsb => if (rmb_started = '0') then csm_functions_next_state <= f_idle; else csm_functions_next_state <= f_tsb; end if; when others => csm_functions_next_state <= f_rst; end case; end process csm_functions_nextstate_proc; ----------------------------------------------------------------- csm_functions_output_proc : process ( adr_sp_i, cnz_detect_in, csm_functions_current_state, d_alu_prio_i, d_regs_out_bak_i, q_a_bak_i, reg_F_bak, shift_rot_asl_out, shift_rot_in, shift_rot_lsr_out, shift_rot_rol_out, shift_rot_ror_out, zw_ALU, zw_ALU1, zw_ALU3, zw_ALU5, zw_b10, zw_b11, zw_b2, zw_b4, zw_b7, zw_b8, zw_b9, zw_din ) ----------------------------------------------------------------- begin -- Default Assignment d_regs_in_o <= X"00"; load_regs_o <= '0'; -- Default Assignment To Internals c_detect_out <= cnz_detect_in(8); cnz_detect_in <= '0' & X"00"; n_detect_out <= cnz_detect_in(7); shift_rot_asl_out <= shift_rot_in (6 downto 0) & '0'; shift_rot_in <= X"00"; shift_rot_l_c_out <= shift_rot_in (7); shift_rot_lsr_out <= '0' & shift_rot_in (7 downto 1); shift_rot_r_c_out <= shift_rot_in (0); shift_rot_rol_out <= shift_rot_in (6 downto 0) & reg_F_bak(0); shift_rot_ror_out <= reg_F_bak(0) & shift_rot_in (7 downto 1); z_detect_out <= NOT(cnz_detect_in(7) OR cnz_detect_in(6) OR cnz_detect_in(5) OR cnz_detect_in(4) OR cnz_detect_in(3) OR cnz_detect_in(2) OR cnz_detect_in(1) OR cnz_detect_in(0)); zw_ALU <= "00" & X"00"; zw_ALU1 <= "00" & X"00"; zw_ALU2 <= "00" & X"00"; zw_ALU3 <= "00" & X"00"; zw_ALU4 <= "00" & X"00"; zw_ALU5 <= "00" & X"00"; zw_ALU6 <= "00" & X"00"; zw_b13 <= (others => '0'); -- Combined Actions case csm_functions_current_state is when f_and => d_regs_in_o <= zw_din AND q_a_bak_i; load_regs_o <= '1'; cnz_detect_in <= '0' & (zw_din AND q_a_bak_i); when f_lda => d_regs_in_o <= zw_din; load_regs_o <= '1'; cnz_detect_in <= '0' & (zw_din); when f_rst => d_regs_in_o <= X"00"; load_regs_o <= '0'; when f_eor => d_regs_in_o <= zw_din XOR q_a_bak_i; load_regs_o <= '1'; cnz_detect_in <= '0' & (zw_din XOR q_a_bak_i); when f_cmp => cnz_detect_in <= unsigned ('0' & d_regs_out_bak_i) + unsigned ('0' & NOT (zw_din)) + 1; when f_ora => d_regs_in_o <= zw_din OR q_a_bak_i; load_regs_o <= '1'; cnz_detect_in <= '0' & (zw_din OR q_a_bak_i); when f_bit1 => cnz_detect_in <= '0' & (zw_din AND q_a_bak_i); when f_bit2 => cnz_detect_in <= '0' & (zw_din AND q_a_bak_i); when f_de_in_a => d_regs_in_o <= unsigned(d_regs_out_bak_i) + unsigned(zw_b4); load_regs_o <= '1'; cnz_detect_in <= '0' & (unsigned(d_regs_out_bak_i) + unsigned(zw_b4)); when f_adc_bin => d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_bak_i) + unsigned ('0' & zw_din) + reg_F_bak(0); when f_sbc_bin => d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(8 downto 0) <= unsigned ('0' & q_a_bak_i) + unsigned ('0' & NOT (zw_din)) + reg_F_bak(0); when f_adc_dec => zw_ALU4(4) <= zw_ALU5(4) OR (zw_ALU5(3) AND zw_ALU5(2)) OR (zw_ALU5(3) AND zw_ALU5(1)); zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_bak_i(7 downto 4)) + unsigned ('0' & zw_din(7 downto 4)) + (zw_ALU3(4)); zw_ALU3(4) <= zw_ALU1(4) OR (zw_ALU1(3) AND zw_ALU1(2)) OR (zw_ALU1(3) AND zw_ALU1(1)); zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_bak_i(3 downto 0)) + unsigned ('0' & zw_din(3 downto 0)) + reg_F_bak(0); when f_adc_dec1 => d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 4) <= unsigned (zw_b10(3 downto 0)) + unsigned (zw_b8(8 downto 5)); zw_ALU(3 downto 0) <= unsigned (zw_b9(3 downto 0)) + unsigned (zw_b7(8 downto 5)); when f_sbc_dec => zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_bak_i(7 downto 4)) + unsigned ("00" & NOT (zw_din(7 downto 4))) + (zw_ALU1(4)); zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_bak_i(3 downto 0)) + unsigned ("00" & NOT (zw_din(3 downto 0))) + reg_F_bak(0); when f_sbc_dec1 => d_regs_in_o <= zw_ALU(7 downto 0); load_regs_o <= '1'; zw_ALU(7 downto 0) <= unsigned (( zw_b8(3 downto 0)) & ( zw_b7(3 downto 0))) - unsigned (zw_b9(7 downto 0)); when f_asla => shift_rot_in <= q_a_bak_i; d_regs_in_o <= shift_rot_asl_out; load_regs_o <= '1'; cnz_detect_in <= '0' & (shift_rot_asl_out); when f_lsra => shift_rot_in <= q_a_bak_i; d_regs_in_o <= shift_rot_lsr_out; load_regs_o <= '1'; cnz_detect_in <= '0' & (shift_rot_lsr_out); when f_rola => shift_rot_in <= q_a_bak_i; d_regs_in_o <= shift_rot_rol_out; load_regs_o <= '1'; cnz_detect_in <= '0' & (shift_rot_rol_out); when f_rora => shift_rot_in <= q_a_bak_i; d_regs_in_o <= shift_rot_ror_out; load_regs_o <= '1'; cnz_detect_in <= '0' & (shift_rot_ror_out); when f_tax => load_regs_o <= '1'; cnz_detect_in <= '0' & (d_regs_out_bak_i); when f_tsx => d_regs_in_o <= adr_sp_i (7 downto 0); load_regs_o <= '1'; cnz_detect_in <= '0' & (adr_sp_i (7 downto 0)); when f_decr => cnz_detect_in <= '0' & (zw_b11); when f_asl => shift_rot_in <= zw_b2; zw_b13 <= shift_rot_asl_out; cnz_detect_in <= '0' & (shift_rot_asl_out); when f_lsr => shift_rot_in <= zw_b2; zw_b13 <= shift_rot_lsr_out; cnz_detect_in <= '0' & (shift_rot_lsr_out); when f_rol => shift_rot_in <= zw_b2; zw_b13 <= shift_rot_rol_out; cnz_detect_in <= '0' & (shift_rot_rol_out); when f_ror => shift_rot_in <= zw_b2; zw_b13 <= shift_rot_ror_out; cnz_detect_in <= '0' & (shift_rot_ror_out); when f_rmb => zw_b13 <= zw_b2 and NOT (d_alu_prio_i); when f_smb => zw_b13 <= zw_b2 or d_alu_prio_i; when f_trb => zw_b13 <= zw_b2 and NOT (q_a_bak_i); cnz_detect_in <= '0' & (zw_b2 and q_a_bak_i); when f_tsb => zw_b13 <= zw_b2 or q_a_bak_i; cnz_detect_in <= '0' & (zw_b2 and q_a_bak_i); when others => null; end case; end process csm_functions_output_proc; ----------------------------------------------------------------- csm_rb_out_clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then csm_rb_out_current_state <= rb_out_idle; elsif (clk_clk_i'event and clk_clk_i = '1') then csm_rb_out_current_state <= csm_rb_out_next_state; end if; end process csm_rb_out_clocked_proc; ----------------------------------------------------------------- csm_rb_out_nextstate_proc : process ( csm_rb_out_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin case csm_rb_out_current_state is when rb_out_idle => if (op_fetch = '0' and (zw_REG_OP = X"8A" or zw_REG_OP = X"9A" or zw_REG_OP = X"BA" or zw_REG_OP = X"86" or zw_REG_OP = X"96" or zw_REG_OP = X"8E" or zw_REG_OP = X"E8" or zw_REG_OP = X"CA" or zw_REG_OP = X"DA" or zw_REG_OP = X"E0" or zw_REG_OP = X"E4" or zw_REG_OP = X"EC")) then csm_rb_out_next_state <= rb_out_01; elsif (op_fetch = '0' and (zw_REG_OP = X"5A" or zw_REG_OP = X"98" or zw_REG_OP = X"84" or zw_REG_OP = X"88" or zw_REG_OP = X"94" or zw_REG_OP = X"8C" or zw_REG_OP = X"C8" or zw_REG_OP = X"C0" or zw_REG_OP = X"C4" or zw_REG_OP = X"CC")) then csm_rb_out_next_state <= rb_out_10; elsif (op_fetch = '0' and (zw_REG_OP = X"9C" or zw_REG_OP = X"9E" or zw_REG_OP = X"64" or zw_REG_OP = X"74")) then csm_rb_out_next_state <= rb_out_11; else csm_rb_out_next_state <= rb_out_idle; end if; when rb_out_01 => if (op_fetch = '1') then csm_rb_out_next_state <= rb_out_idle; else csm_rb_out_next_state <= rb_out_01; end if; when rb_out_10 => if (op_fetch = '1') then csm_rb_out_next_state <= rb_out_idle; else csm_rb_out_next_state <= rb_out_10; end if; when rb_out_11 => if (op_fetch = '1') then csm_rb_out_next_state <= rb_out_idle; else csm_rb_out_next_state <= rb_out_11; end if; when others => csm_rb_out_next_state <= rb_out_idle; end case; end process csm_rb_out_nextstate_proc; ----------------------------------------------------------------- csm_rb_out_output_proc : process ( csm_rb_out_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin -- Default Assignment sel_rb_out_o <= "00"; -- Combined Actions case csm_rb_out_current_state is when rb_out_idle => sel_rb_out_o <= "00"; if (op_fetch = '0' and (zw_REG_OP = X"8A" or zw_REG_OP = X"9A" or zw_REG_OP = X"BA" or zw_REG_OP = X"86" or zw_REG_OP = X"96" or zw_REG_OP = X"8E" or zw_REG_OP = X"E8" or zw_REG_OP = X"CA" or zw_REG_OP = X"DA" or zw_REG_OP = X"E0" or zw_REG_OP = X"E4" or zw_REG_OP = X"EC")) then sel_rb_out_o <= "01"; elsif (op_fetch = '0' and (zw_REG_OP = X"5A" or zw_REG_OP = X"98" or zw_REG_OP = X"84" or zw_REG_OP = X"88" or zw_REG_OP = X"94" or zw_REG_OP = X"8C" or zw_REG_OP = X"C8" or zw_REG_OP = X"C0" or zw_REG_OP = X"C4" or zw_REG_OP = X"CC")) then sel_rb_out_o <= "10"; elsif (op_fetch = '0' and (zw_REG_OP = X"9C" or zw_REG_OP = X"9E" or zw_REG_OP = X"64" or zw_REG_OP = X"74")) then sel_rb_out_o <= "11"; end if; when rb_out_01 => sel_rb_out_o <= "01"; when rb_out_10 => sel_rb_out_o <= "10"; when rb_out_11 => sel_rb_out_o <= "11"; when others => null; end case; end process csm_rb_out_output_proc; ----------------------------------------------------------------- csm_reg_clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then csm_reg_current_state <= reg_idle; elsif (clk_clk_i'event and clk_clk_i = '1') then csm_reg_current_state <= csm_reg_next_state; end if; end process csm_reg_clocked_proc; ----------------------------------------------------------------- csm_reg_nextstate_proc : process ( csm_reg_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin case csm_reg_current_state is when reg_idle => if (op_fetch = '0' and (zw_REG_OP = X"FA" or zw_REG_OP = X"BA" or zw_REG_OP = X"AA" or zw_REG_OP = X"A2" or zw_REG_OP = X"A6" or zw_REG_OP = X"B6" or zw_REG_OP = X"AE" or zw_REG_OP = X"BE" or zw_REG_OP = X"E8" or zw_REG_OP = X"CA")) then csm_reg_next_state <= reg_01; elsif (op_fetch = '0' and (zw_REG_OP = X"A8" or zw_REG_OP = X"7A" or zw_REG_OP = X"A0" or zw_REG_OP = X"A4" or zw_REG_OP = X"B4" or zw_REG_OP = X"AC" or zw_REG_OP = X"BC" or zw_REG_OP = X"C8" or zw_REG_OP = X"88")) then csm_reg_next_state <= reg_10; elsif (op_fetch = '0' and (zw_REG_OP = X"9A")) then csm_reg_next_state <= reg_11; else csm_reg_next_state <= reg_idle; end if; when reg_10 => if (op_fetch = '1') then csm_reg_next_state <= reg_idle; else csm_reg_next_state <= reg_10; end if; when reg_11 => if (op_fetch = '1') then csm_reg_next_state <= reg_idle; else csm_reg_next_state <= reg_11; end if; when reg_01 => if (op_fetch = '1') then csm_reg_next_state <= reg_idle; else csm_reg_next_state <= reg_01; end if; when others => csm_reg_next_state <= reg_idle; end case; end process csm_reg_nextstate_proc; ----------------------------------------------------------------- csm_reg_output_proc : process ( csm_reg_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin -- Default Assignment sel_reg_o <= "00"; -- Combined Actions case csm_reg_current_state is when reg_idle => sel_reg_o<= "00"; if (op_fetch = '0' and (zw_REG_OP = X"FA" or zw_REG_OP = X"BA" or zw_REG_OP = X"AA" or zw_REG_OP = X"A2" or zw_REG_OP = X"A6" or zw_REG_OP = X"B6" or zw_REG_OP = X"AE" or zw_REG_OP = X"BE" or zw_REG_OP = X"E8" or zw_REG_OP = X"CA")) then sel_reg_o <= "01"; elsif (op_fetch = '0' and (zw_REG_OP = X"A8" or zw_REG_OP = X"7A" or zw_REG_OP = X"A0" or zw_REG_OP = X"A4" or zw_REG_OP = X"B4" or zw_REG_OP = X"AC" or zw_REG_OP = X"BC" or zw_REG_OP = X"C8" or zw_REG_OP = X"88")) then sel_reg_o <= "10"; elsif (op_fetch = '0' and (zw_REG_OP = X"9A")) then sel_reg_o <= "11"; end if; when reg_10 => sel_reg_o <= "10"; when reg_11 => sel_reg_o <= "11"; when reg_01 => sel_reg_o <= "01"; when others => null; end case; end process csm_reg_output_proc; ----------------------------------------------------------------- csm_rb_in_clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then csm_rb_in_current_state <= rb_in_idle; elsif (clk_clk_i'event and clk_clk_i = '1') then csm_rb_in_current_state <= csm_rb_in_next_state; end if; end process csm_rb_in_clocked_proc; ----------------------------------------------------------------- csm_rb_in_nextstate_proc : process ( csm_rb_in_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin case csm_rb_in_current_state is when rb_in_idle => if (op_fetch = '0' and (zw_REG_OP = X"A8" or zw_REG_OP = X"AA")) then csm_rb_in_next_state <= rb_in_00; elsif (op_fetch = '0' and (zw_REG_OP = X"98")) then csm_rb_in_next_state <= rb_in_01; elsif (op_fetch = '0' and (zw_REG_OP = X"8A")) then csm_rb_in_next_state <= rb_in_10; else csm_rb_in_next_state <= rb_in_idle; end if; when rb_in_01 => if (op_fetch = '1') then csm_rb_in_next_state <= rb_in_idle; else csm_rb_in_next_state <= rb_in_01; end if; when rb_in_10 => if (op_fetch = '1') then csm_rb_in_next_state <= rb_in_idle; else csm_rb_in_next_state <= rb_in_10; end if; when rb_in_00 => if (op_fetch = '1') then csm_rb_in_next_state <= rb_in_idle; else csm_rb_in_next_state <= rb_in_00; end if; when others => csm_rb_in_next_state <= rb_in_idle; end case; end process csm_rb_in_nextstate_proc; ----------------------------------------------------------------- csm_rb_in_output_proc : process ( csm_rb_in_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin -- Default Assignment sel_rb_in_o <= "00"; -- Combined Actions case csm_rb_in_current_state is when rb_in_idle => sel_rb_in_o <= "11"; if (op_fetch = '0' and (zw_REG_OP = X"A8" or zw_REG_OP = X"AA")) then sel_rb_in_o <= "00"; elsif (op_fetch = '0' and (zw_REG_OP = X"98")) then sel_rb_in_o <= "01"; elsif (op_fetch = '0' and (zw_REG_OP = X"8A")) then sel_rb_in_o <= "10"; end if; when rb_in_01 => sel_rb_in_o <= "01"; when rb_in_10 => sel_rb_in_o <= "10"; when rb_in_00 => sel_rb_in_o <= "00"; when others => null; end case; end process csm_rb_in_output_proc; ----------------------------------------------------------------- csm_add_value_clocked_proc : process ( clk_clk_i, rst_rst_n_i ) ----------------------------------------------------------------- begin if (rst_rst_n_i = '0') then csm_add_value_current_state <= add_val_idle; elsif (clk_clk_i'event and clk_clk_i = '1') then csm_add_value_current_state <= csm_add_value_next_state; end if; end process csm_add_value_clocked_proc; ----------------------------------------------------------------- csm_add_value_nextstate_proc : process ( csm_add_value_current_state, op_fetch, zw_REG_OP ) ----------------------------------------------------------------- begin case csm_add_value_current_state is when add_val_idle => if (op_fetch = '0' and (zw_REG_OP = X"C6" or zw_REG_OP = X"D6" or zw_REG_OP = X"CE" or zw_REG_OP = X"DE" or zw_REG_OP = X"CA" or zw_REG_OP = X"88" or zw_REG_OP = X"3A")) then csm_add_value_next_state <= add_val; else csm_add_value_next_state <= add_val_idle; end if; when add_val => if (op_fetch = '1') then csm_add_value_next_state <= add_val_idle; else csm_add_value_next_state <= add_val; end if; when others => csm_add_value_next_state <= add_val_idle; end case; end process csm_add_value_nextstate_proc; ----------------------------------------------------------------- csm_add_value_output_proc : process ( csm_add_value_current_state ) ----------------------------------------------------------------- begin -- Default Assignment To Internals zw_b4 <= X"00"; -- Combined Actions case csm_add_value_current_state is when add_val_idle => zw_b4 <= X"01"; when add_val => zw_b4 <= X"FF"; when others => null; end case; end process csm_add_value_output_proc; -- Concurrent Statements -- Clocked output assignments sync_o <= sync_o_cld; end fsm;