OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] [trunk/] [html/] [01_Introduction_and_Overview.html] - Rev 2

Compare with Previous | Blame | View Log

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
"http://www.w3.org/TR/html4/strict.dtd">
<HTML>
<HEAD>
<TITLE>html/Introduction_and_Overview</TITLE>
<META NAME="generator" CONTENT="HTML::TextToHTML v2.46">
<LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css">
</HEAD>
<BODY>
<P><table class="ttop"><th class="ttop"></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="02_Top_Level.html">Next Lesson</a></th></table>
<hr>
 
<H1><A NAME="section_1">1 INTRODUCTION AND OVERVIEW</A></H1>
 
<P>This lecture describes in detail how you can design a CPU (actually
an embedded system) in VHDL.
 
<P>The CPU has an instruction set similar to the instruction set of the
popular 8-bit CPUs made by <STRONG>Atmel</STRONG>. The instruction set is described in 
<A HREF="http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf">http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf</A>. We use
an existing CPU so that we can reuse a software tool chain (<STRONG>avr-gcc</STRONG>)
for this kind of CPU and focus on the hardware aspects of the design.
At the end of the lecture, however, you will be able to design your own
CPU with a different instruction set.
 
<P>We will not implement the full instruction set; only the fraction needed
to explain the principles, and to run a simple "Hello world" program (and
probably most C programs) will be described.
 
<H2><A NAME="section_1_1">1.1 Prerequisites</A></H2>
 
<P>Initially you will need two programs:
 
<UL>
  <LI><STRONG>ghdl</STRONG> from <A HREF="http://ghdl.free.fr">http://ghdl.free.fr</A> (a free VHDL compiler and simulator) and
  <LI><STRONG>gtkwave</STRONG> from <A HREF="http://gtkwave.sourceforge.net">http://gtkwave.sourceforge.net</A> (a free visualization tool
for the output of ghdl).
</UL>
<P>These two programs allow you to design the CPU and simulate its functions.
 
<P>Later on, you will need a FPGA toolchain for creating FPGA design files
and to perform timing simulations. For this lecture we assume that the
free <STRONG>Xilinx Webpack</STRONG> tool chain is used (<A HREF="http://www.xilinx.com">http://www.xilinx.com</A>).
The latest version of the Xilinx Webpack provides ISE 11 (as of Nov. 2009)
but we used ISE 10.1 because we used an FPGA board providing a good old
Spartan 2E FPGA (actually an xc2s300e device) which is no longer supported
in ISE 11.
 
<P>Once the CPU design is finished, you need a C compiler that generates code
for the AVR CPU. For downloading <STRONG>avr-gcc</STRONG>, start here:
 
<P><A HREF="http://www.avrfreaks.net/wiki/index.php/Documentation:AVR_GCC#AVR-GCC_on_Unix_and_Linux">http://www.avrfreaks.net/wiki/index.php/Documentation:AVR_GCC#AVR-GCC_on_Unix_and_Linux</A>
 
<P>In order to try out the CPU, you will need some FPGA board
and a programming cable. We used a Memec "Spartan-IIE LC Development Kit"
board and an Avnet "Parallel Cable 3" for this purpose.
These days you will want to use a more recent development environment.
When the hardware runs, the final thing to get is a software toolchain,
for example <STRONG>avr-gcc</STRONG> for the instruction set and memory layout 
used in this lecture. Optional, but rather helpful, is <STRONG>eclipse</STRONG>
(<A HREF="http://www.eclipse.org">http://www.eclipse.org</A>) with the AVR plugin.
 
<P>Another important prerequisite is that the reader is familiar with
VHDL to some extent. You do not need to be a VHDL expert in order
to follow this lecture, but you should not be a VHDL novice either.
 
<H2><A NAME="section_1_2">1.2 Other useful links.</A></H2>
 
<P>A good introduction into VHDL design with open source tools can
be found here:
 
<P><A HREF="http://www.armadeus.com/wiki/index.php?title=How_to_make_a_VHDL_design_in_Ubuntu/Debian">http://www.armadeus.com/wiki/index.php?title=How_to_make_a_VHDL_design_in_Ubuntu/Debian</A>
 
<H2><A NAME="section_1_3">1.3 Structure of this Lecture</A></H2>
 
<P>This lecture is organized as a sequence of lessons. The first lessons will
describe the VHDL files of the CPU design in a top-down fashion.
 
<P>Then follows a lesson on how to compile, simulate and build the design.
 
<P>Finally there is a listing of all design files with line numbers.
Pieces of these design files will be spread over
the different lessons and explained there in detail. In the end, all code
lines in the appendix should have been explained, with the exception of
comments, empty lines and the like. Repetitions such as the structure
of VHDL files or different opcodes that are implemented in the same way,
will only be described once.
 
<P>All source files are provided (without line numbers) in a tar file
that is stored next to this lecture.
 
<H2><A NAME="section_1_4">1.4 Naming Conventions</A></H2>
 
<P>In all lessons and in the VHDL source files, the following conventions
are used:
 
<P>VHDL entities and components and VHDL keywords are written in <STRONG>lowercase</STRONG>.
Signal names and variables are written in <STRONG>UPPERCASE</STRONG>.
Each signal has a prefix according to the following rules:
 
<TABLE>
<TR><TD>I_</TD><TD>for inputs of a VHDL entity.
</TD></TR><TR><TD>Q_</TD><TD>for outputs of a VHDL entity.
</TD></TR><TR><TD>L_</TD><TD>for local signals that are generated by a VHDL construct (e.g. by a signal assignment).
</TD></TR><TR><TD>x_</TD><TD>with an uppercase x for signals <STRONG>generated</STRONG> by an instantiated entity.
</TD></TR>
</TABLE>
<P>For every instantiated component we choose an uppercase letter x (other than
I, L, or Q). All signals driven by the component then get the prefix <STRONG>Q_</STRONG>
(if the instantiated component drives an output of the entity being defined)
or the prefix <STRONG>x_</STRONG> (if the component drives an internal signal).
 
<P>Apart from the prefix, we try to keep the name of a signal the
same across different VHDL files. Unless the prefix matters, we will
use the signal name <STRONG>without its prefix</STRONG> in our descriptions.
 
<P>Another convention is that we use one VHLD source file for every
entity that we define and that the name of the file (less the
.vhd extension) matches the entity name.
 
<H2><A NAME="section_1_5">1.5 Directory Structure</A></H2>
 
<P>Create a directory of your choice. In that directory, <STRONG>mkdir</STRONG> the following
sub-directories:
 
<TABLE>
<TR><TD>app</TD><TD>for building the program that will run on the CPU (i.e. <STRONG>hello.c</STRONG>)
</TD></TR><TR><TD>simu</TD><TD>for object files generated by <STRONG>ghdl</STRONG>
</TD></TR><TR><TD>src</TD><TD>for VHDL source files of the CPU and <STRONG>avr_fpga.ucf</STRONG>
</TD></TR><TR><TD>test</TD><TD>for a VHDL testbench
</TD></TR><TR><TD>tools</TD><TD>for tools <STRONG>end_conv</STRONG> and <STRONG>make_mem</STRONG>
</TD></TR><TR><TD>work</TD><TD>working directory for <STRONG>ghdl</STRONG>
</TD></TR>
</TABLE>
<P>Initially the directory should look like this:
 
<pre class="cmd">
 
# ls -R .
./app:
hello.c
 
./simu:
 
./src:
alu.vhd
avr_fpga.ucf
avr_fpga.vhd
baudgen.vhd
common.vhd
COPYING
cpu_core.vhd
data_mem.vhd
data_path.vhd
io.vhd
opc_deco.vhd
opc_fetch.vhd
prog_mem_content.vhd
prog_mem.vhd
reg_16.vhd
register_file.vhd
segment7.vhd
status_reg.vhd
uart_rx.vhd
uart_tx.vhd
uart.vhd
 
./test:
RAMB4_S4_S4.vhd
test_tb.vhd
 
./tools:
end_conv.cc
make_mem.cc
 
./work:
 
</pre>
<P>
 
<H2><A NAME="section_1_6">1.6 Other Useful Tools</A></H2>
 
<P>This lecture was prepared with 3 excellent tools:
 
<UL>
  <LI><STRONG>vim</STRONG> 7.1.38 for preparing the text of the lecture,
  <LI><STRONG>txt2html</STRONG> 2.46 for converting the text into html, and
  <LI><STRONG>dia</STRONG> 0.5 for drawing the figures.
</UL>
<P><hr><BR>
<table class="ttop"><th class="ttop"></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="02_Top_Level.html">Next Lesson</a></th></table>
</BODY>
</HTML>
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.