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<P><table class="ttop"><th class="tpre"><a href="10_Listing_of_alu_vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="12_Listing_of_baudgen.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">11 LISTING OF avr_fpga.vhd</A></H1>
 
<pre class="vhdl">
 
  1	-------------------------------------------------------------------------------
  2	-- 
  3	-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
  4	-- 
  5	--  This code is free software: you can redistribute it and/or modify
  6	--  it under the terms of the GNU General Public License as published by
  7	--  the Free Software Foundation, either version 3 of the License, or
  8	--  (at your option) any later version.
  9	--
 10	--  This code is distributed in the hope that it will be useful,
 11	--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 12	--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13	--  GNU General Public License for more details.
 14	--
 15	--  You should have received a copy of the GNU General Public License
 16	--  along with this code (see the file named COPYING).
 17	--  If not, see http://www.gnu.org/licenses/.
 18	--
 19	-------------------------------------------------------------------------------
 20	-------------------------------------------------------------------------------
 21	--
 22	-- Module Name:     avr_fpga - Behavioral 
 23	-- Create Date:     13:51:24 11/07/2009 
 24	-- Description:     top level of a CPU
 25	--
 26	-------------------------------------------------------------------------------
 27	
 28	library IEEE;
 29	use IEEE.STD_LOGIC_1164.ALL;
 30	use IEEE.STD_LOGIC_ARITH.ALL;
 31	use IEEE.STD_LOGIC_UNSIGNED.ALL;
 32	
 33	entity avr_fpga is
 34	    port (  I_CLK_100   : in  std_logic;
 35	            I_SWITCH    : in  std_logic_vector(9 downto 0);
 36	            I_RX        : in  std_logic;
 37	
 38	            Q_LEDS      : out std_logic_vector(3 downto 0);
 39	            Q_7_SEGMENT : out std_logic_vector(6 downto 0);
 40	            Q_TX        : out std_logic);
 41	end avr_fpga;
 42	
 43	architecture Behavioral of avr_fpga is
 44	
 45	component cpu_core
 46	    port (  I_CLK       : in  std_logic;
 47	            I_CLR       : in  std_logic;
 48	            I_INTVEC    : in  std_logic_vector( 5 downto 0);
 49	            I_DIN       : in  std_logic_vector( 7 downto 0);
 50	
 51	            Q_OPC       : out std_logic_vector(15 downto 0);
 52	            Q_PC        : out std_logic_vector(15 downto 0);
 53	            Q_DOUT      : out std_logic_vector( 7 downto 0);
 54	            Q_ADR_IO    : out std_logic_vector( 7 downto 0);
 55	            Q_RD_IO     : out std_logic;
 56	            Q_WE_IO     : out std_logic);
 57	end component;
 58	
 59	signal  C_PC            : std_logic_vector(15 downto 0);
 60	signal  C_OPC           : std_logic_vector(15 downto 0);
 61	signal  C_ADR_IO        : std_logic_vector( 7 downto 0);
 62	signal  C_DOUT          : std_logic_vector( 7 downto 0);
 63	signal  C_RD_IO         : std_logic;
 64	signal  C_WE_IO         : std_logic;
 65	
 66	component io
 67	    port (  I_CLK       : in  std_logic;
 68	            I_CLR       : in  std_logic;
 69	            I_ADR_IO    : in  std_logic_vector( 7 downto 0);
 70	            I_DIN       : in  std_logic_vector( 7 downto 0);
 71	            I_RD_IO     : in  std_logic;
 72	            I_WE_IO     : in  std_logic;
 73	            I_SWITCH    : in  std_logic_vector( 7 downto 0);
 74	            I_RX        : in  std_logic;
 75	
 76	            Q_7_SEGMENT : out std_logic_vector( 6 downto 0);
 77	            Q_DOUT      : out std_logic_vector( 7 downto 0);
 78	            Q_INTVEC    : out std_logic_vector(5 downto 0);
 79	            Q_LEDS      : out std_logic_vector( 1 downto 0);
 80	            Q_TX        : out std_logic);
 81	
 82	end component;
 83	
 84	signal N_INTVEC         : std_logic_vector( 5 downto 0);
 85	signal N_DOUT           : std_logic_vector( 7 downto 0);
 86	signal N_TX             : std_logic;
 87	signal N_7_SEGMENT      : std_logic_vector( 6 downto 0);
 88	
 89	component segment7
 90	    port ( I_CLK        : in  std_logic;
 91	
 92	           I_CLR        : in  std_logic;
 93	           I_OPC        : in  std_logic_vector(15 downto 0);
 94	           I_PC         : in  std_logic_vector(15 downto 0);
 95	
 96	           Q_7_SEGMENT  : out std_logic_vector( 6 downto 0));
 97	end component;
 98	
 99	signal S_7_SEGMENT      : std_logic_vector( 6 downto 0);
100	
101	signal L_CLK            : std_logic := '0';
102	signal L_CLK_CNT        : std_logic_vector( 2 downto 0) := "000";
103	signal L_CLR            : std_logic;            -- reset,  active low
104	signal L_CLR_N          : std_logic := '0';     -- reset,  active low
105	signal L_C1_N           : std_logic := '0';     -- switch debounce, active low
106	signal L_C2_N           : std_logic := '0';     -- switch debounce, active low
107	
108	begin
109	
110	    cpu : cpu_core
111	    port map(   I_CLK       => L_CLK,
112	                I_CLR       => L_CLR,
113	                I_DIN       => N_DOUT,
114	                I_INTVEC    => N_INTVEC,
115	
116	                Q_ADR_IO    => C_ADR_IO,
117	                Q_DOUT      => C_DOUT,
118	                Q_OPC       => C_OPC,
119	                Q_PC        => C_PC,
120	                Q_RD_IO     => C_RD_IO,
121	                Q_WE_IO     => C_WE_IO);
122	
123	    ino : io
124	    port map(   I_CLK       => L_CLK,
125	                I_CLR       => L_CLR,
126	                I_ADR_IO    => C_ADR_IO,
127	                I_DIN       => C_DOUT,
128	                I_RD_IO     => C_RD_IO,
129	                I_RX        => I_RX,
130	                I_SWITCH    => I_SWITCH(7 downto 0),
131	                I_WE_IO     => C_WE_IO,
132	
133	                Q_7_SEGMENT => N_7_SEGMENT,
134	                Q_DOUT      => N_DOUT,
135	                Q_INTVEC    => N_INTVEC,
136	                Q_LEDS      => Q_LEDS(1 downto 0),
137	                Q_TX        => N_TX);
138	
139	    seg : segment7
140	    port map(   I_CLK       => L_CLK,
141	                I_CLR       => L_CLR,
142	                I_OPC       => C_OPC,
143	                I_PC        => C_PC,
144	
145	                Q_7_SEGMENT => S_7_SEGMENT);
146	    
147	    -- input clock scaler
148	    --
149	    clk_div : process(I_CLK_100)
150	    begin
151	        if (rising_edge(I_CLK_100)) then
152	            L_CLK_CNT <= L_CLK_CNT + "001";
153	            if (L_CLK_CNT = "001") then
154	                L_CLK_CNT <= "000";
155	                L_CLK <= not L_CLK;
156	            end if;
157	        end if;
158	    end process;
159	    
160	    -- reset button debounce process
161	    --
162	    deb : process(L_CLK)
163	    begin
164	        if (rising_edge(L_CLK)) then
165	            -- switch debounce
166	            if ((I_SWITCH(8) = '0') or (I_SWITCH(9) = '0')) then    -- pushed
167	                L_CLR_N <= '0';
168	                L_C2_N  <= '0';
169	                L_C1_N  <= '0';
170	            else                                                    -- released
171	                L_CLR_N <= L_C2_N;
172	                L_C2_N  <= L_C1_N;
173	                L_C1_N  <= '1';
174	            end if;
175	        end if;
176	    end process;
177	
178	    L_CLR <= not L_CLR_N;
179	
180	    Q_LEDS(2) <= I_RX;
181	    Q_LEDS(3) <= N_TX;
182	    Q_7_SEGMENT  <= N_7_SEGMENT when (I_SWITCH(7) = '1') else S_7_SEGMENT;
183	    Q_TX <= N_TX;
184	
185	end Behavioral;
186	
<pre class="filename">
src/avr_fpga.vhd
</pre></pre>
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