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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML> <HEAD> <TITLE>html/Listing_of_RAMB4_S4_S4.vhd</TITLE> <META NAME="generator" CONTENT="HTML::TextToHTML v2.46"> <LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css"> </HEAD> <BODY> <P><table class="ttop"><th class="tpre"><a href="27_Listing_of_uart_tx.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="29_Listing_of_test_tb.vhd.html">Next Lesson</a></th></table> <hr> <H1><A NAME="section_1">28 LISTING OF RAMB4_S4_S4.vhd</A></H1> <pre class="vhdl"> 1 ------------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann 4 -- 5 -- This code is free software: you can redistribute it and/or modify 6 -- it under the terms of the GNU General Public License as published by 7 -- the Free Software Foundation, either version 3 of the License, or 8 -- (at your option) any later version. 9 -- 10 -- This code is distributed in the hope that it will be useful, 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 -- GNU General Public License for more details. 14 -- 15 -- You should have received a copy of the GNU General Public License 16 -- along with this code (see the file named COPYING). 17 -- If not, see http://www.gnu.org/licenses/. 18 -- 19 ------------------------------------------------------------------------------- 20 ------------------------------------------------------------------------------- 21 -- 22 -- Module Name: prog_mem - Behavioral 23 -- Create Date: 14:09:04 10/30/2009 24 -- Description: a block memory module 25 -- 26 ------------------------------------------------------------------------------- 27 28 library IEEE; 29 use IEEE.STD_LOGIC_1164.ALL; 30 use IEEE.STD_LOGIC_ARITH.ALL; 31 use IEEE.STD_LOGIC_UNSIGNED.ALL; 32 33 entity RAMB4_S4_S4 is 34 generic(INIT_00 : bit_vector := X"00000000000000000000000000000000" 35 & "00000000000000000000000000000000"; 36 INIT_01 : bit_vector := X"00000000000000000000000000000000" 37 & X"00000000000000000000000000000000"; 38 INIT_02 : bit_vector := X"00000000000000000000000000000000" 39 & X"00000000000000000000000000000000"; 40 INIT_03 : bit_vector := X"00000000000000000000000000000000" 41 & X"00000000000000000000000000000000"; 42 INIT_04 : bit_vector := X"00000000000000000000000000000000" 43 & X"00000000000000000000000000000000"; 44 INIT_05 : bit_vector := X"00000000000000000000000000000000" 45 & X"00000000000000000000000000000000"; 46 INIT_06 : bit_vector := X"00000000000000000000000000000000" 47 & X"00000000000000000000000000000000"; 48 INIT_07 : bit_vector := X"00000000000000000000000000000000" 49 & X"00000000000000000000000000000000"; 50 INIT_08 : bit_vector := X"00000000000000000000000000000000" 51 & X"00000000000000000000000000000000"; 52 INIT_09 : bit_vector := X"00000000000000000000000000000000" 53 & X"00000000000000000000000000000000"; 54 INIT_0A : bit_vector := X"00000000000000000000000000000000" 55 & X"00000000000000000000000000000000"; 56 INIT_0B : bit_vector := X"00000000000000000000000000000000" 57 & X"00000000000000000000000000000000"; 58 INIT_0C : bit_vector := X"00000000000000000000000000000000" 59 & X"00000000000000000000000000000000"; 60 INIT_0D : bit_vector := X"00000000000000000000000000000000" 61 & X"00000000000000000000000000000000"; 62 INIT_0E : bit_vector := X"00000000000000000000000000000000" 63 & X"00000000000000000000000000000000"; 64 INIT_0F : bit_vector := X"00000000000000000000000000000000" 65 & X"00000000000000000000000000000000"); 66 67 port( ADDRA : in std_logic_vector(9 downto 0); 68 ADDRB : in std_logic_vector(9 downto 0); 69 CLKA : in std_ulogic; 70 CLKB : in std_ulogic; 71 DIA : in std_logic_vector(3 downto 0); 72 DIB : in std_logic_vector(3 downto 0); 73 ENA : in std_ulogic; 74 ENB : in std_ulogic; 75 RSTA : in std_ulogic; 76 RSTB : in std_ulogic; 77 WEA : in std_ulogic; 78 WEB : in std_ulogic; 79 80 DOA : out std_logic_vector(3 downto 0); 81 DOB : out std_logic_vector(3 downto 0)); 82 end RAMB4_S4_S4; 83 84 architecture Behavioral of RAMB4_S4_S4 is 85 86 function cv(A : bit) return std_logic is 87 begin 88 if (A = '1') then return '1'; 89 else return '0'; 90 end if; 91 end; 92 93 function cv1(A : std_logic) return bit is 94 begin 95 if (A = '1') then return '1'; 96 else return '0'; 97 end if; 98 end; 99 100 signal DATA : bit_vector(4095 downto 0) := 101 INIT_0F & INIT_0E & INIT_0D & INIT_0C & INIT_0B & INIT_0A & INIT_09 & INIT_08 & 102 INIT_07 & INIT_06 & INIT_05 & INIT_04 & INIT_03 & INIT_02 & INIT_01 & INIT_00; 103 104 begin 105 106 process(CLKA, CLKB) 107 begin 108 if (rising_edge(CLKA)) then 109 if (ENA = '1') then 110 DOA(3) <= cv(DATA(conv_integer(ADDRA & "11"))); 111 DOA(2) <= cv(DATA(conv_integer(ADDRA & "10"))); 112 DOA(1) <= cv(DATA(conv_integer(ADDRA & "01"))); 113 DOA(0) <= cv(DATA(conv_integer(ADDRA & "00"))); 114 if (WEA = '1') then 115 DATA(conv_integer(ADDRA & "11")) <= cv1(DIA(3)); 116 DATA(conv_integer(ADDRA & "10")) <= cv1(DIA(2)); 117 DATA(conv_integer(ADDRA & "01")) <= cv1(DIA(1)); 118 DATA(conv_integer(ADDRA & "00")) <= cv1(DIA(0)); 119 end if; 120 end if; 121 end if; 122 123 if (rising_edge(CLKB)) then 124 if (ENB = '1') then 125 DOB(3) <= cv(DATA(conv_integer(ADDRB & "11"))); 126 DOB(2) <= cv(DATA(conv_integer(ADDRB & "10"))); 127 DOB(1) <= cv(DATA(conv_integer(ADDRB & "01"))); 128 DOB(0) <= cv(DATA(conv_integer(ADDRB & "00"))); 129 if (WEB = '1') then 130 DATA(conv_integer(ADDRB & "11")) <= cv1(DIB(3)); 131 DATA(conv_integer(ADDRB & "10")) <= cv1(DIB(2)); 132 DATA(conv_integer(ADDRB & "01")) <= cv1(DIB(1)); 133 DATA(conv_integer(ADDRB & "00")) <= cv1(DIB(0)); 134 end if; 135 end if; 136 end if; 137 end process; 138 139 end Behavioral; 140 <pre class="filename"> test/RAMB4_S4_S4.vhd </pre></pre> <P> <P><hr><BR> <table class="ttop"><th class="tpre"><a href="27_Listing_of_uart_tx.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="29_Listing_of_test_tb.vhd.html">Next Lesson</a></th></table> </BODY> </HTML>