Subversion Repositories debouncer_vhdl

Release 13.1 - xst O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: debounce_atlys_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "debounce_atlys_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "debounce_atlys_top"
Output Format                      : NGC
Target Device                      : xc6slx45-2-csg324

---- Source Options
Top Module Name                    : debounce_atlys_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Gray
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : No
ROM Extraction                     : No
Shift Register Extraction          : NO
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Area
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\grp_debouncer.vhd" into library work
Parsing entity <grp_debouncer>.
Parsing architecture <rtl> of entity <grp_debouncer>.
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" into library work
Parsing entity <debounce_atlys_top>.
Parsing architecture <rtl> of entity <debounce_atlys_top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <debounce_atlys_top> (architecture <rtl>) from library <work>.

Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 71: Net <dbg[15]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <debounce_atlys_top>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".
WARNING:Xst:2935 - Signal 'dbg<15>', unconnected in block 'debounce_atlys_top', is tied to its initial value (0).
    Found 7-bit register for signal <led_o>.
    Summary:
        inferred   7 D-type flip-flop(s).
Unit <debounce_atlys_top> synthesized.

Synthesizing Unit <grp_debouncer>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".
        N = 7
        CNT_VAL = 5000
    Found 7-bit register for signal <reg_A>.
    Found 7-bit register for signal <reg_B>.
    Found 1-bit register for signal <strb_reg>.
    Found 7-bit register for signal <reg_out>.
    Found 13-bit register for signal <cnt_reg>.
    Found 14-bit adder for signal <n0026> created at line 167.
    Found 7-bit comparator not equal for signal <n0009> created at line 192
    Found 7-bit comparator not equal for signal <n0011> created at line 194
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred  35 D-type flip-flop(s).
        inferred   2 Comparator(s).
Unit <grp_debouncer> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 14-bit adder                                          : 1
# Registers                                            : 6
 1-bit register                                        : 1
 13-bit register                                       : 1
 7-bit register                                        : 4
# Comparators                                          : 2
 7-bit comparator not equal                            : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <grp_debouncer>.
The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>.
Unit <grp_debouncer> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 13-bit up counter                                     : 1
# Registers                                            : 29
 Flip-Flops                                            : 29
# Comparators                                          : 2
 7-bit comparator not equal                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <debounce_atlys_top> ...

Optimizing unit <grp_debouncer> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block debounce_atlys_top, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 42
 Flip-Flops                                            : 42

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : debounce_atlys_top.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 73
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 12
#      LUT3                        : 1
#      LUT4                        : 9
#      LUT6                        : 23
#      MUXCY                       : 12
#      VCC                         : 1
#      XORCY                       : 13
# FlipFlops/Latches                : 42
#      FD                          : 28
#      FDE                         : 14
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 30
#      IBUF                        : 7
#      OBUF                        : 23

Device utilization summary:
---------------------------

Selected Device : 6slx45csg324-2 


Slice Logic Utilization: 
 Number of Slice Registers:              42  out of  54576     0%  
 Number of Slice LUTs:                   46  out of  27288     0%  
    Number used as Logic:                46  out of  27288     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     67
   Number with an unused Flip Flop:      25  out of     67    37%  
   Number with an unused LUT:            21  out of     67    31%  
   Number of fully used LUT-FF pairs:    21  out of     67    31%  
   Number of unique control sets:         3

IO Utilization: 
 Number of IOs:                          31
 Number of bonded IOBs:                  31  out of    218    14%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
gclk_i                             | BUFGP                  | 42    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 4.717ns (Maximum Frequency: 211.999MHz)
   Minimum input arrival time before clock: 2.127ns
   Maximum output required time after clock: 4.380ns
   Maximum combinational path delay: 4.965ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
  Clock period: 4.717ns (frequency: 211.999MHz)
  Total number of paths / destination ports: 713 / 49
-------------------------------------------------------------------------
Delay:               4.717ns (Levels of Logic = 3)
  Source:            Inst_sw_debouncer/cnt_reg_0 (FF)
  Destination:       Inst_sw_debouncer/strb_reg (FF)
  Source Clock:      gclk_i rising
  Destination Clock: gclk_i rising

  Data Path: Inst_sw_debouncer/cnt_reg_0 to Inst_sw_debouncer/strb_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.525   1.181  Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)
     LUT6:I0->O            8   0.254   1.052  Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
     LUT3:I1->O           14   0.250   1.127  Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)
     LUT6:I5->O            1   0.254   0.000  Inst_sw_debouncer/strb_next6 (Inst_sw_debouncer/strb_next)
     FD:D                      0.074          Inst_sw_debouncer/strb_reg
    ----------------------------------------
    Total                      4.717ns (1.357ns logic, 3.360ns route)
                                       (28.8% logic, 71.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Offset:              2.127ns (Levels of Logic = 1)
  Source:            sw_i<6> (PAD)
  Destination:       Inst_sw_debouncer/reg_A_6 (FF)
  Destination Clock: gclk_i rising

  Data Path: sw_i<6> to Inst_sw_debouncer/reg_A_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.328   0.725  sw_i_6_IBUF (dbg_o_6_OBUF)
     FD:D                      0.074          Inst_sw_debouncer/reg_A_6
    ----------------------------------------
    Total                      2.127ns (1.402ns logic, 0.725ns route)
                                       (65.9% logic, 34.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
  Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Offset:              4.380ns (Levels of Logic = 1)
  Source:            Inst_sw_debouncer/strb_reg (FF)
  Destination:       dbg_o<14> (PAD)
  Source Clock:      gclk_i rising

  Data Path: Inst_sw_debouncer/strb_reg to dbg_o<14>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               8   0.525   0.943  Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
     OBUF:I->O                 2.912          dbg_o_14_OBUF (dbg_o<14>)
    ----------------------------------------
    Total                      4.380ns (3.437ns logic, 0.943ns route)
                                       (78.5% logic, 21.5% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay:               4.965ns (Levels of Logic = 2)
  Source:            sw_i<6> (PAD)
  Destination:       dbg_o<6> (PAD)

  Data Path: sw_i<6> to dbg_o<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.328   0.725  sw_i_6_IBUF (dbg_o_6_OBUF)
     OBUF:I->O                 2.912          dbg_o_6_OBUF (dbg_o<6>)
    ----------------------------------------
    Total                      4.965ns (4.240ns logic, 0.725ns route)
                                       (85.4% logic, 14.6% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock gclk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i         |    4.717|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.57 secs
 
--> 

Total memory usage is 185320 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)