OpenCores
URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top.twr] - Rev 6

Go to most recent revision | Compare with Previous | Blame | View Log

--------------------------------------------------------------------------------
Release 13.1 Trace  (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
3 -fastpaths -xml debounce_atlys_top.twx debounce_atlys_top.ncd -o
debounce_atlys_top.twr debounce_atlys_top.pcf -ucf debounce_atlys.ucf

Design file:              debounce_atlys_top.ncd
Physical constraint file: debounce_atlys_top.pcf
Device,package,speed:     xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock gclk_i
------------+------------+------------+------------+------------+------------------+--------+
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
------------+------------+------------+------------+------------+------------------+--------+
sw_i<0>     |    5.038(R)|      SLOW  |   -2.761(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<1>     |    5.576(R)|      SLOW  |   -3.098(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<2>     |    5.317(R)|      SLOW  |   -2.953(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<3>     |    4.491(R)|      SLOW  |   -2.388(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<4>     |    2.742(R)|      SLOW  |   -1.466(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<5>     |    4.819(R)|      SLOW  |   -2.715(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<6>     |    4.336(R)|      SLOW  |   -2.454(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<7>     |    5.893(R)|      SLOW  |   -3.333(R)|      FAST  |gclk_i_BUFGP      |   0.000|
------------+------------+------------+------------+------------+------------------+--------+

Clock gclk_i to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
------------+-----------------+------------+-----------------+------------+------------------+--------+
dbg_o<8>    |        11.232(R)|      SLOW  |         4.814(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<9>    |        11.480(R)|      SLOW  |         4.979(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<10>   |        11.254(R)|      SLOW  |         4.861(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<11>   |        11.049(R)|      SLOW  |         4.732(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<12>   |        11.559(R)|      SLOW  |         5.013(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<13>   |        11.939(R)|      SLOW  |         5.209(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<14>   |        12.377(R)|      SLOW  |         5.519(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<15>   |        12.060(R)|      SLOW  |         5.330(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<0>    |         9.814(R)|      SLOW  |         4.065(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<1>    |         9.656(R)|      SLOW  |         3.955(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<2>    |         9.469(R)|      SLOW  |         3.865(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<3>    |         9.929(R)|      SLOW  |         4.132(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<4>    |         9.577(R)|      SLOW  |         3.889(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<5>    |        17.272(R)|      SLOW  |         8.413(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<6>    |        11.323(R)|      SLOW  |         4.861(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<7>    |        10.605(R)|      SLOW  |         4.453(R)|      FAST  |gclk_i_BUFGP      |   0.000|
strb_o      |        13.397(R)|      SLOW  |         6.237(R)|      FAST  |gclk_i_BUFGP      |   0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock gclk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i         |    4.464|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
sw_i<0>        |dbg_o<0>       |   16.209|
sw_i<1>        |dbg_o<1>       |   16.941|
sw_i<2>        |dbg_o<2>       |   16.803|
sw_i<3>        |dbg_o<3>       |    9.229|
sw_i<4>        |dbg_o<4>       |    7.980|
sw_i<5>        |dbg_o<5>       |    8.917|
sw_i<6>        |dbg_o<6>       |    9.026|
sw_i<7>        |dbg_o<7>       |   15.558|
---------------+---------------+---------+


Analysis completed Thu Aug 11 00:07:33 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 178 MB



Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.