URL
https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk
Subversion Repositories debouncer_vhdl
[/] [debouncer_vhdl/] [trunk/] [bench/] [debounce_atlys_top_summary.html] - Rev 10
Compare with Previous | Blame | View Log
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status</B></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD>debounce_vhdl_bench.xise</TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> <TD> No Errors </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD>debounce_atlys_top</TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD>Synthesized</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD>xc6slx45-2csg324</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD> </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD> </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD>Balanced</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> <TD> All Signals Completely Routed</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> <TD> <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> <TD> </TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> <TD>0 </TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#FFFF99'> <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> <TD ALIGN=RIGHT>42</TD> <TD ALIGN=RIGHT>54,576</TD> <TD ALIGN=RIGHT>1%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> <TD ALIGN=RIGHT>42</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> <TD ALIGN=RIGHT>37</TD> <TD ALIGN=RIGHT>27,288</TD> <TD ALIGN=RIGHT>1%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> <TD ALIGN=RIGHT>36</TD> <TD ALIGN=RIGHT>27,288</TD> <TD ALIGN=RIGHT>1%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> <TD ALIGN=RIGHT>18</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> <TD ALIGN=RIGHT>11</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> <TD ALIGN=RIGHT>7</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>6,408</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD> <TD ALIGN=RIGHT>1</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD> <TD ALIGN=RIGHT>1</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> <TD ALIGN=RIGHT>19</TD> <TD ALIGN=RIGHT>6,822</TD> <TD ALIGN=RIGHT>1%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> <TD ALIGN=RIGHT>56</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD> <TD ALIGN=RIGHT>20</TD> <TD ALIGN=RIGHT>56</TD> <TD ALIGN=RIGHT>35%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD> <TD ALIGN=RIGHT>19</TD> <TD ALIGN=RIGHT>56</TD> <TD ALIGN=RIGHT>33%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD> <TD ALIGN=RIGHT>17</TD> <TD ALIGN=RIGHT>56</TD> <TD ALIGN=RIGHT>30%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD> <TD ALIGN=RIGHT>3</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD> <TD ALIGN=RIGHT>6</TD> <TD ALIGN=RIGHT>54,576</TD> <TD ALIGN=RIGHT>1%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> <TD ALIGN=RIGHT>31</TD> <TD ALIGN=RIGHT>218</TD> <TD ALIGN=RIGHT>14%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD> <TD ALIGN=RIGHT>31</TD> <TD ALIGN=RIGHT>31</TD> <TD ALIGN=RIGHT>100%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>116</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>232</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>32</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>32</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>16</TD> <TD ALIGN=RIGHT>6%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD> <TD ALIGN=RIGHT>1</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD> <TD ALIGN=RIGHT>0</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>8</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>376</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>376</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>376</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>4</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>256</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>8</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>4</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>58</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>2</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>2</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>4</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> <TD ALIGN=RIGHT>2.37</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> <TD>0 (Setup: 0, Hold: 0)</TD> <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> <TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> All Signals Completely Routed</TD> <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> <TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> <TD> <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> <TD BGCOLOR='#FFFF99'><B> </B></TD> <TD COLSPAN='2'> </TD> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>seg 15. ago 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>seg 19. set 14:56:36 2011</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qui 11. ago 21:31:43 2011</TD></TR> </TABLE> <br><center><b>Date Generated:</b> 09/19/2011 - 15:37:38</center> </BODY></HTML>