Subversion Repositories dma_axi

//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:52 2011
//--
//-- Source file: dma_core_axim_timeout.v
//---------------------------------------------------------
 
 
 
module dma_axi32_core0_axim_timeout(clk,reset,VALID,READY,ID,axim_timeout_num,axim_timeout);
 
   input               clk;
   input               reset;
 
   input               VALID;
   input               READY;
   input [`CMD_BITS-1:0]      ID;
 
   output [2:0]           axim_timeout_num;
   output               axim_timeout;
 
 
 
   reg [`TIMEOUT_BITS-1:0]    counter;
 
 
   assign               axim_timeout_num = ID[2:0];
 
   assign               axim_timeout = (counter == 'd0);
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       counter <= #1 {`TIMEOUT_BITS{1'b1}};
     else if (VALID & READY)
       counter <= #1 {`TIMEOUT_BITS{1'b1}};
     else if (VALID)
       counter <= #1 counter - 1'b1;
 
 
 
endmodule