Subversion Repositories dma_axi

//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:36:53 2011
//--
//-- Source file: dma_apb_mux.v
//---------------------------------------------------------
 
 
 
module  dma_axi64_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg);
 
   input                 clk;
   input                 reset;
 
   input                 pclken;
   input                 psel;
   input                 penable;
   input          pwrite;
   input [12:11]      paddr;
   output [31:0]         prdata;
   output          pslverr;
   output          pready;
 
   output          psel0;
   input [31:0]      prdata0;
   input           pslverr0;
 
   output          psel1;
   input [31:0]      prdata1;
   input           pslverr1;
 
   output          psel_reg;
   input [31:0]      prdata_reg;
   input           pslverr_reg;
 
   wire [31:0]          prdata_pre;
   wire          pslverr_pre;
 
 
   reg              pready;
 
 
   assign          psel0    = pclken & psel & (paddr[12:11] == 2'b00);
   assign          psel1    = pclken & psel & (paddr[12:11] == 2'b01);
   assign          psel_reg = pclken & psel & (paddr[12] == 1'b1);
 
   assign          prdata_pre  = prdata0 | prdata1 | prdata_reg;
   assign          pslverr_pre = pslverr0 | pslverr1 | pslverr_reg;
 
   assign          prdata = prdata_pre;
   assign          pslverr = pslverr_pre;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       pready <= #1 1'b0;
     else if (pclken)
       pready <= #1 psel & (~penable);
 
 
endmodule