OpenCores
URL https://opencores.org/ocsvn/esoc/esoc/trunk

Subversion Repositories esoc

[/] [esoc/] [trunk/] [Simulation/] [Logs/] [5/] [esoc_control_test_log_5.txt] - Rev 41

Compare with Previous | Blame | View Log

ESOC Control -> start generating read/write cycles on control interface

 Search bookmarks: 
 TBENCH CTRL   DARB   SARB   SENG   SCNT
 P0CTRL P1CTRL P2CTRL P3CTRL P4CTRL P5CTRL P6CTRL P7CTRL 
 P0CNT  P1CNT  P2CNT  P3CNT  P4CNT  P5CNT  P6CNT  P7CNT 
 status: ERROR

========================================================
 Status & Control ESOC Control                (CTRL)
========================================================

========================================================
 Status & Control ESOC Data Bus Arbiter       (DARB)
========================================================
 Port weight

========================================================
 Status & Control ESOC Search Bus Arbiter     (SARB)
========================================================
 Port weight

========================================================
 Status & Control ESOC Search Engine          (SENG)
========================================================
 Status and Control
mw 8810 00000020
========================================================
 Status & Control ESOC Port 0               (P0CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 0000 00000800, expected 00000800, status: OK
 Configuration
mw 0002 0400001B
mr 0002 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 0005 000005F2
mr 0005 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 003a 00000000
mw 003b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 0180 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 0181 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 0197 C0000001
mw 0197 00000001
mr 0197 40000000, expected 40000000, status: OK
mw 0197 C00007FF
mw 0197 000007FF
mr 0197 40000000, expected 40000000, status: OK
--------------------------------------------------------
 Status & Control ESOC Port Processor
--------------------------------------------------------
 Status and Control
mr 0190 00000000, expected 00000000, status: OK
========================================================
 Status & Control ESOC Port 1               (P1CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 0800 00000800, expected 00000800, status: OK
 Configuration
mw 0802 0400001B
mr 0802 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 0805 000005F2
mr 0805 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 083a 00000000
mw 083b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 0980 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 0981 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 0997 C0000001
mw 0997 00000001
mr 0997 40000000, expected 40000000, status: OK
mw 0997 C00007FF
mw 0997 000007FF
mr 0997 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Port 2               (P2CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 1000 00000800, expected 00000800, status: OK
 Configuration
mw 1002 0400001B
mr 1002 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 1005 000005F2
mr 1005 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 103a 00000000
mw 103b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 1180 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 1181 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 1197 C0000001
mw 1197 00000001
mr 1197 40000000, expected 40000000, status: OK
mw 1197 C00007FF
mw 1197 000007FF
mr 1197 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Port 3               (P3CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 1800 00000800, expected 00000800, status: OK
 Configuration
mw 1802 0400001B
mr 1802 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 1805 000005F2
mr 1805 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 183a 00000000
mw 183b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 1980 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 1981 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 1997 C0000001
mw 1997 00000001
mr 1997 40000000, expected 40000000, status: OK
mw 1997 C00007FF
mw 1997 000007FF
mr 1997 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Port 4               (P4CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 2000 00000800, expected 00000800, status: OK
 Configuration
mw 2002 0400001B
mr 2002 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 2005 000005F2
mr 2005 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 203a 00000000
mw 203b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 2180 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 2181 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 2197 C0000001
mw 2197 00000001
mr 2197 40000000, expected 40000000, status: OK
mw 2197 C0000FFF
mw 2197 00000FFF
mr 2197 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Port 5               (P5CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 2800 00000800, expected 00000800, status: OK
 Configuration
mw 2802 0400001B
mr 2802 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 2805 000005F2
mr 2805 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 283a 00000000
mw 283b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 2980 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 2981 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 2997 C0000001
mw 2997 00000001
mr 2997 40000000, expected 40000000, status: OK
mw 2997 C0000FFF
mw 2997 00000FFF
mr 2997 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Port 6               (P6CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 3000 00000800, expected 00000800, status: OK
 Configuration
mw 3002 0400001B
mr 3002 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 3005 000005F2
mr 3005 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 303a 00000000
mw 303b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 3180 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 3181 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 3197 C0000001
mw 3197 00000001
mr 3197 40000000, expected 40000000, status: OK
mw 3197 C0000FFF
mw 3197 00000FFF
mr 3197 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Port 7               (P7CTRL)
========================================================
--------------------------------------------------------
 Status & Control ESOC Port MAC
--------------------------------------------------------
 Revision
mr 3800 00000800, expected 00000800, status: OK
 Configuration
mw 3802 0400001B
mr 3802 0400001B, expected 0400001B, status: OK
 Maximum Frame Length
mw 3805 000005F2
mr 3805 000005F2, expected 000005F2, status: OK
 Word alignment disable
mw 383a 00000000
mw 383b 00000000
--------------------------------------------------------
 Status & Control ESOC Port MAL
--------------------------------------------------------
 Status and Control
mr 3980 00000001, expected 00000001, status: OK
 Default VLAN ID
mr 3981 00000001, expected 00000001, status: OK
 VLAN ID Membership
mw 3997 C0000001
mw 3997 00000001
mr 3997 40000000, expected 40000000, status: OK
mw 3997 C0000FFF
mw 3997 00000FFF
mr 3997 40000000, expected 40000000, status: OK
========================================================
 Status & Control ESOC Test Bench             (TBENCH)
========================================================
 RGMII Interface Enable
mw FF00 000000FF
mw FF00 000000FF

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.