Subversion Repositories fat_32_file_parser

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:09:44 11/18/2014 
-- Design Name: 
-- Module Name:    lifo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lifo is
	Generic (	G_LOG2_DEPTH  	: natural := 6;
					G_DATA_SIZE		: natural := 8	); -- LOG2(lifo depth)
    Port ( CLK_IN 			: in  STD_LOGIC;
           RESET_IN 			: in  STD_LOGIC;
           CACHE_ADDR_IN	: in  STD_LOGIC;
           GOTO_CACHE_IN 	: in  STD_LOGIC;
           WR_DATA_IN 		: in  STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0);
           WR_EN_IN 			: in  STD_LOGIC;
           RD_DATA_OUT 		: out STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0);
           RD_EN_IN 			: in  STD_LOGIC;
           EMPTY_OUT 		: out STD_LOGIC;
			  FULL_OUT			: out STD_LOGIC);
 
	attribute ram_style : string; 
	attribute ram_style of lifo : entity is "block";
 
end lifo;
 
architecture Behavioral of lifo is
 
	COMPONENT TDP_RAM
		Generic (G_DATA_A_SIZE 	:natural :=32;
					G_ADDR_A_SIZE	:natural :=9;
					G_RELATION		:natural :=3;
					G_INIT_FILE		:string :="");--log2(SIZE_A/SIZE_B)
		Port ( CLK_A_IN 	: in  STD_LOGIC;
				 WE_A_IN 	: in  STD_LOGIC;
				 ADDR_A_IN 	: in  STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0);
				 DATA_A_IN	: in  STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
				 DATA_A_OUT	: out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
				 CLK_B_IN 	: in  STD_LOGIC;
				 WE_B_IN 	: in  STD_LOGIC;
				 ADDR_B_IN 	: in  STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0);
				 DATA_B_IN 	: in  STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0);
				 DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0));
	END COMPONENT;
 
subtype slv is std_logic_vector;
 
constant C_max : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '1');
constant C_min : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '0');
 
signal wr_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := C_min;
signal rd_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := C_min;
signal cached_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '0');
signal zeros : std_logic_vector((G_DATA_SIZE - 1) downto 0) := (others => '0');
 
begin
 
	process(CLK_IN)
	begin
		if rising_edge(CLK_IN) then
			if RESET_IN = '1' then
				wr_addr <= (others => '0');
				rd_addr <= (others => '0');
			elsif GOTO_CACHE_IN = '0' then
				if WR_EN_IN = '1' then
					if wr_addr /= C_max then
						wr_addr <= wr_addr + 1;
					end if;
					if rd_addr /= C_max and wr_addr /= C_min then
						rd_addr <= rd_addr + 1;
					end if;
				elsif RD_EN_IN = '1' then
					if rd_addr /= C_min then
						rd_addr <= rd_addr - 1;
					end if;
					if wr_addr /= C_min and rd_addr /= C_max then
						wr_addr <= wr_addr - 1;
					end if;
				end if;
			else
				wr_addr <= cached_addr + 1;
				rd_addr <= cached_addr;
			end if;
		end if;
	end process;
 
	process(CLK_IN)
	begin
		if rising_edge(CLK_IN) then	
			if CACHE_ADDR_IN = '1' then
				cached_addr <= rd_addr;
			elsif RESET_IN = '1' then
				cached_addr <= (others => '0');
			end if;
		end if;
	end process;
 
	process(CLK_IN)
	begin
		if rising_edge(CLK_IN) then
			if RESET_IN = '1' then
				EMPTY_OUT <= '1';
			elsif WR_EN_IN = '1' or GOTO_CACHE_IN = '1' then
				EMPTY_OUT <= '0';
			elsif wr_addr = C_min then
				EMPTY_OUT <= '1';
			end if;
		end if;
	end process;
 
	process(CLK_IN)
	begin
		if rising_edge(CLK_IN) then	
			if RD_EN_IN = '1' then
				FULL_OUT <= '0';
			elsif rd_addr = C_max then
				FULL_OUT <= '1';
			end if;
		end if;
	end process;
 
	TDP_RAM_Inst : TDP_RAM
		Generic Map (	G_DATA_A_SIZE 	=> G_DATA_SIZE,
							G_ADDR_A_SIZE	=> G_LOG2_DEPTH,
							G_RELATION		=> 0, --log2(SIZE_A/SIZE_B)
							G_INIT_FILE		=> "") 
		Port Map ( 	CLK_A_IN 	=> CLK_IN, 
						WE_A_IN 		=> WR_EN_IN,
						ADDR_A_IN 	=> slv(wr_addr),
						DATA_A_IN	=> WR_DATA_IN,
						DATA_A_OUT	=> open,
						CLK_B_IN 	=> CLK_IN,
						WE_B_IN 		=> '0',
						ADDR_B_IN 	=> slv(rd_addr),
						DATA_B_IN 	=> zeros,
						DATA_B_OUT 	=> RD_DATA_OUT);
 
end Behavioral;