Subversion Repositories floating_point_adder_subtractor

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity addsub is
port
	( input_a,input_b : in std_logic_vector(32 downto 0);
	  msb_ab : in std_logic_vector(1 downto 0);
	  clk,reset,finish_shift,add_sub : in std_logic;
	  finish_addsub : out std_logic;
      output_result : out std_logic_vector(33 downto 0)
	);	-- input_a larger after swap, inpu_b shifted according to 
end addsub;				     
 
architecture addsub of addsub is
begin
process(clk,input_a,input_b,clk,reset,finish_shift,add_sub,msb_ab)
variable man_a,man_b,temp : std_logic_vector(24 downto 0);
variable exp_a : std_logic_vector(7 downto 0);
variable msb_a,msb_b : std_logic;
begin
 
if (reset='1' or finish_shift='0') then
	output_result<="0000000000000000000000000000000000";
	finish_addsub<='0';
 
elsif( reset='0' and finish_shift='1' and input_a="0000000000000000000000000000000000" and 
     input_b="0000000000000000000000000000000000" ) then
 
	output_result<="0000000000000000000000000000000000";
	finish_addsub<='1';
elsif( reset='0' and finish_shift='1') then
 
    	exp_a:=input_a(31 downto 24);
	man_a:='0' & input_a(23 downto 0);
	man_b:='0' & input_b(23 downto 0);
	msb_a:=input_a(32);
	msb_b:=input_b(32);
 
	if (add_sub='0') then  -- subtraction
	  if( msb_ab="00" or msb_ab="11")then	    --if both same sign then subtract
	  temp:= man_a - man_b;					    --mantissa
	  elsif( msb_ab="01" or msb_ab="10") then   --if un equal sign, add mantissa
	  temp:= man_a + man_b;	
	  end if;
   	end if;
 
   	if (add_sub='1') then
	  if( msb_ab="00" or msb_ab="11")then
	  temp:= man_a + man_b;
	  elsif( msb_ab="01" or msb_ab="10") then
	  temp:= man_a - man_b;	
	  end if;
	end if;
 
output_result <= msb_a & exp_a & temp;
finish_addsub <= '1';
end if;
end process;
end addsub;