Subversion Repositories floating_point_adder_subtractor

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity normalize is
port (
		input : in std_logic_vector(33 downto 0);
		clk,finish_add,reset : in std_logic;
		output_addsub : out std_logic_vector(31 downto 0);
		finish_nor_addsub : out std_logic
	  );
end normalize;
 
architecture normalize of normalize is
begin
process(clk,input,finish_add,reset)
variable mantissa : std_logic_vector(24 downto 0);
variable exp : std_logic_vector(7 downto 0);
variable nor_mantissa : std_logic_vector(22 downto 0);
begin
if clk='1' and clk'event then
if(reset='1' or finish_add='0') then
finish_nor_addsub <= '0';
output_addsub <= "00000000000000000000000000000000";
elsif (reset='0' and finish_add='1' and input="0000000000000000000000000000000000") then
finish_nor_addsub <= '1';
output_addsub <= "00000000000000000000000000000000";
elsif (reset='0' and finish_add='1') then
	  mantissa:=input(24 downto 0);
	  exp:=input(32 downto 25);				--mantissa overflow,shit to right
	  if (mantissa(24)='1') then			--add exponent
	     mantissa(23 downto 0):=mantissa(24 downto 1);
	     exp:=exp + 1;
	  else
	a : for i in 1 to 10 loop				--if concanated not equal to 1 then
	    if (mantissa(23)='0') then			--shitft to left,minus exponent
	    mantissa(23 downto 1):=mantissa(22 downto 0);
	    exp:=exp - 1;
	    else
	    exit a;
	    end if;
	    end loop;
	 end if;
	 output_addsub <= input(33) & exp & mantissa(22 downto 0);
	 finish_nor_addsub <= '1';
	end if;
end if;
end process;
end normalize;