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##############################################################
#
# Xilinx Core Generator version K.39
# Date: Fri Sep 18 11:15:52 2009
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vsx55
SET devicefamily = virtex4
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1148
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -12
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Floating-point family Xilinx,_Inc. 4.0
# END Select
# BEGIN Parameters
CSET a_precision_type=Single
CSET add_sub_value=Add
CSET c_a_exponent_width=8
CSET c_a_fraction_width=24
CSET c_compare_operation=Programmable
CSET c_has_ce=false
CSET c_has_divide_by_zero=false
CSET c_has_invalid_op=false
CSET c_has_operation_nd=true
CSET c_has_operation_rfd=false
CSET c_has_overflow=false
CSET c_has_rdy=true
CSET c_has_sclr=true
CSET c_has_underflow=false
CSET c_latency=11
CSET c_mult_usage=Full_Usage
CSET c_optimization=Speed_Optimized
CSET c_rate=1
CSET c_result_exponent_width=8
CSET c_result_fraction_width=24
CSET c_speed=Maximum_speed
CSET component_name=sp_fp_add
CSET maximum_latency=true
CSET operation_type=Add_Subtract
CSET result_precision_type=Single
# END Parameters
GENERATE
# CRC: c74fce74