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##############################################################
#
# Xilinx Core Generator version K.39
# Date: Fri Sep 18 11:26:16 2009
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vsx55
SET devicefamily = virtex4
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1148
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -12
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Comparator family Xilinx,_Inc. 9.0
# END Select
# BEGIN Parameters
CSET aclr=false
CSET ainitval=0
CSET aset=false
CSET ce=false
CSET cepriority=Sync_Overrides_CE
CSET component_name=comp_eq_000000000000
CSET constantbport=true
CSET constantbportvalue=000000000000
CSET datatype=Unsigned
CSET nonregisteredoutput=false
CSET operation=eq
CSET pipelinestages=0
CSET radix=2
CSET registeredoutput=true
CSET sclr=true
CSET sset=false
CSET syncctrlpriority=Reset_Overrides_Set
CSET width=12
# END Parameters
GENERATE
# CRC: 78b96c50