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<b><font face="Helvetica, Arial"><font color="#BF0000"><font size=+2>Project
Name: Floating Point Unit</font></font></font></b>
<p><font size=-1>(See change Log at bottom of page for changes/updates)</font>
<br> 
<p><u><font size=+1>Description</font></u>
<p>This is a single precision floating point unit. It is fully IEEE 754
compliant. It can currently perform Add/Sub,  Mul and Divide operations,
as well as integer to floating point and floating point to integer conversions.
It supports four rounding modes: Round to Nearest Even, Round to Zero,
Round to +INF and Round to -INF.
<p>There is now also a separate FP compare unit. It is located in the fpu/fcmp
directory.
<br> 
<p><u><font size=+1>Motivation</font></u>
<ul>
<li>
A 100% IEEE 754 compliant Floating Point Unit</li>
 
<li>
Usable by the OR1K CPU</li>
 
<li>
Options to extend the core</li>
 
<li>
Free !</li>
</ul>
 
<p><br><u><font size=+1>Compatibility</font></u>
<p>To the best of my knowledge the FPU is 100% IEEE 754 compliant. I have
run over 14Mil. test vectors on it,  that where generated using the
SoftFloat library by John R. Hauser, which can be found at: <a href="http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html">http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html</a>
<br>The test pattern generator is included with the distribution.
<br> 
<p><u><font size=+1>Performance</font></u>
<ul>
<li>
Single cycle execution</li>
 
<li>
4 stage pipeline (this will probably be change in the future)</li>
</ul>
 
<p><br><u><font size=+1>Implementing the Core</font></u>
<p>It is very difficult to partition such a complex piece of hardware for
optimal pipe lining. Therefore you will need a synthesis tool that has
a "retiring" feature to obtain best results.
<p>Actual Add/Sub, Multiply and Divide cores must be replaced in the primitives.v
file, or your synthesis tool must be able to synthesize them for you. I
might fix this in the future.
<br> 
<p><u><font size=+1>Status</font></u>
<p>Second version of the core is released. Included with the release is
also a  test bench and a test pattern generator.
<p>I won't be doing any more work on the core in the near future, except
for bug fixes.
<p>The core can be downloaded from OpenCores CVS via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb</a>
or via <a href="/cvsmodule.shtml">cvsget</a> (use fpu for module name)
<br> 
<p><u><font size=+1>To-Do</font></u>
<p>Things that need to be done:
<ul>
<li>
Add a remainder function</li>
 
<li>
Predict leading zeros to improve performance of post normalize unit</li>
</ul>
 
<p><br><u><font size=+1>Author / Maintainer</font></u>
<p>I have been doing ASIC design, verification and synthesis for over 15
years. I hope you find this cores useful. Please send me a note if you
intend to use it  !
<p>Many thanks to Damjan Lampret for his support and motivation !
<p>Rudolf Usselmann
<br><a href="mailto:rudi@asics.ws_NOSPAM">rudi@asics.ws_NOSPAM</a>
<br><a href="http://www.asics.ws">www.asics.ws</a>
<p>Feel free to send me comments, suggestions and bug reports.
<br> 
<p><u><font size=+1>Change Log</font></u>
<p>9/16/00 RU
<br>- Added FP compare unit
<p>9/15/00 RU
<br>- Added int to float and float to int conversion
<br>- Fixed documentation
<p>9/13/200 RU
<br>- Initial release
<br> 
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