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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [basic_tester/] [1.0/] [ip_xact/] [basic_tester_tx.1.0.xml] - Rev 179

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<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus211:06:25 27.06.2012-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
        <spirit:vendor>TUT</spirit:vendor>
        <spirit:library>ip.hwp.communication</spirit:library>
        <spirit:name>basic_tester_tx</spirit:name>
        <spirit:version>1.0</spirit:version>
        <spirit:description>Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data. 

This IP-XACT component is fixed to 32-bit data and 5-bit command.

Works only in simulation because configuration is done with ASCII file.</spirit:description>
        <spirit:busInterfaces>
                <spirit:busInterface>
                        <spirit:name>clock</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>CLK</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>clk</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>hibi_master</spirit:name>
                        <spirit:description>Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.</spirit:description>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
                        <spirit:master/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>COMM</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>4</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>agent_comm_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>4</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>DATA</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>agent_data_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>31</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>WE</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>agent_we_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>AV</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>agent_av_out</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>hibi_slave</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>ONE_P</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>agent_one_p_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>FULL</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>agent_full_in</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
                <spirit:busInterface>
                        <spirit:name>reset</spirit:name>
                        <spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
                        <spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
                        <spirit:slave/>
                        <spirit:connectionRequired>false</spirit:connectionRequired>
                        <spirit:portMaps>
                                <spirit:portMap>
                                        <spirit:logicalPort>
                                                <spirit:name>RESETn</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:logicalPort>
                                        <spirit:physicalPort>
                                                <spirit:name>rst_n</spirit:name>
                                                <spirit:vector>
                                                        <spirit:left>0</spirit:left>
                                                        <spirit:right>0</spirit:right>
                                                </spirit:vector>
                                        </spirit:physicalPort>
                                </spirit:portMap>
                        </spirit:portMaps>
                        <spirit:bitsInLau>8</spirit:bitsInLau>
                        <spirit:endianness>little</spirit:endianness>
                </spirit:busInterface>
        </spirit:busInterfaces>
        <spirit:model>
                <spirit:views>
                        <spirit:view>
                                <spirit:name>rtl</spirit:name>
                                <spirit:envIdentifier>VHDL::</spirit:envIdentifier>
                                <spirit:fileSetRef>
                                        <spirit:localName>rtl</spirit:localName>
                                </spirit:fileSetRef>
                        </spirit:view>
                </spirit:views>
                <spirit:ports>
                        <spirit:port>
                                <spirit:name>agent_av_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>agent_comm_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>4</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>agent_data_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                        <spirit:vector>
                                                <spirit:left>31</spirit:left>
                                                <spirit:right>0</spirit:right>
                                        </spirit:vector>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>agent_full_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>agent_one_p_in</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>agent_we_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>clk</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>done_out</spirit:name>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>out</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                        <spirit:port>
                                <spirit:name>rst_n</spirit:name>
                                <spirit:description>Active low</spirit:description>
                                <spirit:wire spirit:allLogicalDirectionsAllowed="false">
                                        <spirit:direction>in</spirit:direction>
                                </spirit:wire>
                                <spirit:vendorExtensions/>
                        </spirit:port>
                </spirit:ports>
                <spirit:modelParameters>
                        <spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped">
                                <spirit:name>comm_width_g</spirit:name>
                                <spirit:value>5</spirit:value>
                        </spirit:modelParameter>
                        <spirit:modelParameter spirit:dataType="string" spirit:usageType="nontyped">
                                <spirit:name>conf_file_g</spirit:name>
                                <spirit:description>File that contains the sent data</spirit:description>
                                <spirit:value>test_tx.txt</spirit:value>
                        </spirit:modelParameter>
                        <spirit:modelParameter spirit:dataType="integer" spirit:usageType="nontyped">
                                <spirit:name>data_width_g</spirit:name>
                                <spirit:value>32</spirit:value>
                        </spirit:modelParameter>
                </spirit:modelParameters>
        </spirit:model>
        <spirit:fileSets>
                <spirit:fileSet>
                        <spirit:name>rtl</spirit:name>
                        <spirit:description>VHDL sources</spirit:description>
                        <spirit:file>
                                <spirit:name>../vhd/txt_util.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../vhd/basic_tester_pkg.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../vhd/basic_tester_tx.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                        </spirit:file>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-check_synthesis</spirit:flags>
                                <spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                </spirit:fileSet>
                <spirit:fileSet>
                        <spirit:name>example_usage</spirit:name>
                        <spirit:description>Instantiates tx, rx and 2 hibi wrappers. Tx sends few values. Rx catches them and checks their contents and reception times.</spirit:description>
                        <spirit:file>
                                <spirit:name>../tb/tb_basic_tester.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Top-level. Generates clock and reset, instantiates basic tester tx+rx and hibi wrappers.</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../vhd/basic_tester_rx.vhd</spirit:name>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:logicalName spirit:default="false">work</spirit:logicalName>
                                <spirit:description>Receiver unit.</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../sim/test_tx.txt</spirit:name>
                                <spirit:userFileType>ASCII</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:description>Contents of transmitted values</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../sim/compile_all.sh</spirit:name>
                                <spirit:userFileType>shell script</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:dependency></spirit:dependency>
                                <spirit:description>Creates VHDL libraries and compiles everything.
</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../sim/tb_basic_tester.do</spirit:name>
                                <spirit:userFileType>Modelsim macro</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:description>Sets up the wave viewer</spirit:description>
                        </spirit:file>
                        <spirit:file>
                                <spirit:name>../sim/test_rx.txt</spirit:name>
                                <spirit:userFileType>ASCII</spirit:userFileType>
                                <spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
                                <spirit:description>Expected values for the receiver
</spirit:description>
                        </spirit:file>
                        <spirit:defaultFileBuilder>
                                <spirit:fileType>vhdlSource</spirit:fileType>
                                <spirit:command>vcom</spirit:command>
                                <spirit:flags>-check_synthesis</spirit:flags>
                                <spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
                        </spirit:defaultFileBuilder>
                        <spirit:dependency>../../../../ip.hwp.storage/fifos</spirit:dependency>
                        <spirit:dependency>../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd</spirit:dependency>
                        <spirit:dependency>../../../hibi/3.0/vhd</spirit:dependency>
                </spirit:fileSet>
        </spirit:fileSets>
        <spirit:vendorExtensions>
                <kactus2:extensions>
                        <kactus2:kts_attributes>
                                <kactus2:kts_productHier>IP</kactus2:kts_productHier>
                                <kactus2:kts_implementation>HW</kactus2:kts_implementation>
                                <kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
                        </kactus2:kts_attributes>
                </kactus2:extensions>
        </spirit:vendorExtensions>
</spirit:component>

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