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/*******************************************************************************
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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
coregenerator_fifo_send YourInstanceName (
        .din(din), // Bus [31 : 0] 
        .rd_clk(rd_clk),
        .rd_en(rd_en),
        .rst(rst),
        .wr_clk(wr_clk),
        .wr_en(wr_en),
        .almost_empty(almost_empty),
        .almost_full(almost_full),
        .dout(dout), // Bus [15 : 0] 
        .empty(empty),
        .full(full));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file coregenerator_fifo_send.v when simulating
// the core, coregenerator_fifo_send. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".