Subversion Repositories gnextrapolator

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:28:12 2012 " "Info: Processing started: Tue Aug 14 00:28:12 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4 " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "96 " "Warning: Found 96 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[14\] 0 " "Info: Pin \"fxx_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[15\] 0 " "Info: Pin \"fxx_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[14\] 0 " "Info: Pin \"fxx1_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[15\] 0 " "Info: Pin \"fxx1_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[14\] 0 " "Info: Pin \"fxx2_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[15\] 0 " "Info: Pin \"fxx2_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[14\] 0 " "Info: Pin \"fxx3_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[15\] 0 " "Info: Pin \"fxx3_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[14\] 0 " "Info: Pin \"fxx4_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[15\] 0 " "Info: Pin \"fxx4_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[14\] 0 " "Info: Pin \"resul_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[15\] 0 " "Info: Pin \"resul_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_i " "Info: Assuming node \"clk_i\" is an undefined clock" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_i" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_i memory altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0 register resultado\[15\] 46.88 MHz 21.332 ns Internal " "Info: Clock \"clk_i\" has Internal fmax of 46.88 MHz between source memory \"altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0\" and destination register \"resultado\[15\]\" (period= 21.332 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.577 ns + Longest memory register " "Info: + Longest memory to register delay is 10.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M512_X24_Y8 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.061 ns) 2.061 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7 2 MEM M512_X24_Y8 6 " "Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.061 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(0.060 ns) 2.987 ns fx~23 3 COMB LCCOMB_X27_Y5_N22 2 " "Info: 3: + IC(0.866 ns) + CELL(0.060 ns) = 2.987 ns; Loc. = LCCOMB_X27_Y5_N22; Fanout = 2; COMB Node = 'fx~23'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.926 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.426 ns) 4.287 ns Add2~37 4 COMB LCCOMB_X23_Y8_N30 6 " "Info: 4: + IC(0.874 ns) + CELL(0.426 ns) = 4.287 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { fx~23 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.426 ns) 5.384 ns Add3~33 5 COMB LCCOMB_X22_Y7_N0 7 " "Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 5.384 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.097 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.570 ns) 6.628 ns Add4~38 6 COMB LCCOMB_X22_Y6_N30 2 " "Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 6.628 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { Add3~33 Add4~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 6.669 ns Add4~42 7 COMB LCCOMB_X22_Y5_N0 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 6.669 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~38 Add4~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 6.710 ns Add4~46 8 COMB LCCOMB_X22_Y5_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 6.710 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~42 Add4~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 6.751 ns Add4~50 9 COMB LCCOMB_X22_Y5_N4 2 " "Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 6.751 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~46 Add4~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 6.895 ns Add4~53 10 COMB LCCOMB_X22_Y5_N6 7 " "Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 6.895 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~50 Add4~53 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.502 ns) 8.074 ns Add8~46 11 COMB LCCOMB_X25_Y5_N6 2 " "Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 8.074 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { Add4~53 Add8~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.115 ns Add8~50 12 COMB LCCOMB_X25_Y5_N8 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 8.115 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~46 Add8~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.156 ns Add8~54 13 COMB LCCOMB_X25_Y5_N10 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 8.156 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~50 Add8~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.197 ns Add8~58 14 COMB LCCOMB_X25_Y5_N12 1 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 8.197 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~54 Add8~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 8.341 ns Add8~61 15 COMB LCCOMB_X25_Y5_N14 1 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 8.341 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add8~58 Add8~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.426 ns) 9.320 ns Add9~61 16 COMB LCCOMB_X26_Y5_N30 2 " "Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 9.320 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.979 ns" { Add8~61 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.355 ns) 10.577 ns resultado\[15\] 17 REG LCFF_X23_Y7_N3 4 " "Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 10.577 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.360 ns ( 50.68 % ) " "Info: Total cell delay = 5.360 ns ( 50.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.217 ns ( 49.32 % ) " "Info: Total interconnect delay = 5.217 ns ( 49.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 {} fx~23 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 0.866ns 0.874ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 2.061ns 0.060ns 0.426ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.176 ns - Smallest " "Info: - Smallest clock skew is 0.176 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.830 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_i\" to destination register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[15\] 3 REG LCFF_X23_Y7_N3 4 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.654 ns - Longest memory " "Info: - Longest clock path from clock \"clk_i\" to source memory is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.526 ns) 2.654 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M512_X24_Y8 16 " "Info: 3: + IC(0.760 ns) + CELL(0.526 ns) = 2.654 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 56.52 % ) " "Info: Total cell delay = 1.500 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.154 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk_i clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.394ns 0.760ns } { 0.000ns 0.974ns 0.000ns 0.526ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk_i clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.394ns 0.760ns } { 0.000ns 0.974ns 0.000ns 0.526ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.161 ns + " "Info: + Micro clock to output delay of source is 0.161 ns" {  } { { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 {} fx~23 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 0.866ns 0.874ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 2.061ns 0.060ns 0.426ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk_i clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.394ns 0.760ns } { 0.000ns 0.974ns 0.000ns 0.526ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "resultado\[15\] extrapolar_i clk_i 12.402 ns register " "Info: tsu for register \"resultado\[15\]\" (data pin = \"extrapolar_i\", clock pin = \"clk_i\") is 12.402 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.128 ns + Longest pin register " "Info: + Longest pin to register delay is 15.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.920 ns) 0.920 ns extrapolar_i 1 PIN PIN_B9 96 " "Info: 1: + IC(0.000 ns) + CELL(0.920 ns) = 0.920 ns; Loc. = PIN_B9; Fanout = 96; PIN Node = 'extrapolar_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.261 ns) + CELL(0.435 ns) 7.616 ns fx~22 2 COMB LCCOMB_X23_Y5_N24 2 " "Info: 2: + IC(6.261 ns) + CELL(0.435 ns) = 7.616 ns; Loc. = LCCOMB_X23_Y5_N24; Fanout = 2; COMB Node = 'fx~22'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.696 ns" { extrapolar_i fx~22 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.403 ns) 8.694 ns Add2~34 3 COMB LCCOMB_X23_Y8_N28 2 " "Info: 3: + IC(0.675 ns) + CELL(0.403 ns) = 8.694 ns; Loc. = LCCOMB_X23_Y8_N28; Fanout = 2; COMB Node = 'Add2~34'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.078 ns" { fx~22 Add2~34 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 8.838 ns Add2~37 4 COMB LCCOMB_X23_Y8_N30 6 " "Info: 4: + IC(0.000 ns) + CELL(0.144 ns) = 8.838 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add2~34 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.426 ns) 9.935 ns Add3~33 5 COMB LCCOMB_X22_Y7_N0 7 " "Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 9.935 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.097 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.570 ns) 11.179 ns Add4~38 6 COMB LCCOMB_X22_Y6_N30 2 " "Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 11.179 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { Add3~33 Add4~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 11.220 ns Add4~42 7 COMB LCCOMB_X22_Y5_N0 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 11.220 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~38 Add4~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 11.261 ns Add4~46 8 COMB LCCOMB_X22_Y5_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 11.261 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~42 Add4~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 11.302 ns Add4~50 9 COMB LCCOMB_X22_Y5_N4 2 " "Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 11.302 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~46 Add4~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 11.446 ns Add4~53 10 COMB LCCOMB_X22_Y5_N6 7 " "Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 11.446 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~50 Add4~53 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.502 ns) 12.625 ns Add8~46 11 COMB LCCOMB_X25_Y5_N6 2 " "Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 12.625 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { Add4~53 Add8~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 12.666 ns Add8~50 12 COMB LCCOMB_X25_Y5_N8 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 12.666 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~46 Add8~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 12.707 ns Add8~54 13 COMB LCCOMB_X25_Y5_N10 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 12.707 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~50 Add8~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 12.748 ns Add8~58 14 COMB LCCOMB_X25_Y5_N12 1 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 12.748 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~54 Add8~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 12.892 ns Add8~61 15 COMB LCCOMB_X25_Y5_N14 1 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 12.892 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add8~58 Add8~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.426 ns) 13.871 ns Add9~61 16 COMB LCCOMB_X26_Y5_N30 2 " "Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 13.871 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.979 ns" { Add8~61 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.355 ns) 15.128 ns resultado\[15\] 17 REG LCFF_X23_Y7_N3 4 " "Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 15.128 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.715 ns ( 31.17 % ) " "Info: Total cell delay = 4.715 ns ( 31.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.413 ns ( 68.83 % ) " "Info: Total interconnect delay = 10.413 ns ( 68.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.128 ns" { extrapolar_i fx~22 Add2~34 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "15.128 ns" { extrapolar_i {} extrapolar_i~combout {} fx~22 {} Add2~34 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 6.261ns 0.675ns 0.000ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 0.920ns 0.435ns 0.403ns 0.144ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.830 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_i\" to destination register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[15\] 3 REG LCFF_X23_Y7_N3 4 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.128 ns" { extrapolar_i fx~22 Add2~34 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "15.128 ns" { extrapolar_i {} extrapolar_i~combout {} fx~22 {} Add2~34 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 6.261ns 0.675ns 0.000ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 0.920ns 0.435ns 0.403ns 0.144ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_i fxx3_o\[14\] fxx3_o\[14\]~reg0 8.310 ns register " "Info: tco from clock \"clk_i\" to destination pin \"fxx3_o\[14\]\" through register \"fxx3_o\[14\]~reg0\" is 8.310 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.842 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to source register is 2.842 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.710 ns) 2.842 ns fxx3_o\[14\]~reg0 3 REG LCFF_X22_Y5_N13 1 " "Info: 3: + IC(0.764 ns) + CELL(0.710 ns) = 2.842 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o\[14\]~reg0'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.474 ns" { clk_i~clkctrl fxx3_o[14]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.25 % ) " "Info: Total cell delay = 1.684 ns ( 59.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.158 ns ( 40.75 % ) " "Info: Total interconnect delay = 1.158 ns ( 40.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.842 ns" { clk_i clk_i~clkctrl fxx3_o[14]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.842 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[14]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.764ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.359 ns + Longest register pin " "Info: + Longest register to pin delay is 5.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fxx3_o\[14\]~reg0 1 REG LCFF_X22_Y5_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o\[14\]~reg0'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[14]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.924 ns) + CELL(2.435 ns) 5.359 ns fxx3_o\[14\] 2 PIN PIN_J5 0 " "Info: 2: + IC(2.924 ns) + CELL(2.435 ns) = 5.359 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'fxx3_o\[14\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { fxx3_o[14]~reg0 fxx3_o[14] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.435 ns ( 45.44 % ) " "Info: Total cell delay = 2.435 ns ( 45.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.924 ns ( 54.56 % ) " "Info: Total interconnect delay = 2.924 ns ( 54.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { fxx3_o[14]~reg0 fxx3_o[14] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.359 ns" { fxx3_o[14]~reg0 {} fxx3_o[14] {} } { 0.000ns 2.924ns } { 0.000ns 2.435ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.842 ns" { clk_i clk_i~clkctrl fxx3_o[14]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.842 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[14]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.764ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { fxx3_o[14]~reg0 fxx3_o[14] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.359 ns" { fxx3_o[14]~reg0 {} fxx3_o[14] {} } { 0.000ns 2.924ns } { 0.000ns 2.435ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "resultado\[15\] rst_i clk_i -1.094 ns register " "Info: th for register \"resultado\[15\]\" (data pin = \"rst_i\", clock pin = \"clk_i\") is -1.094 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.830 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to destination register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[15\] 3 REG LCFF_X23_Y7_N3 4 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.172 ns + " "Info: + Micro hold delay of destination is 0.172 ns" {  } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.096 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns rst_i 1 PIN PIN_M21 98 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_M21; Fanout = 98; PIN Node = 'rst_i'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(0.858 ns) 4.096 ns resultado\[15\] 2 REG LCFF_X23_Y7_N3 4 " "Info: 2: + IC(2.254 ns) + CELL(0.858 ns) = 4.096 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" {  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.112 ns" { rst_i resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.842 ns ( 44.97 % ) " "Info: Total cell delay = 1.842 ns ( 44.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.254 ns ( 55.03 % ) " "Info: Total interconnect delay = 2.254 ns ( 55.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { rst_i resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "4.096 ns" { rst_i {} rst_i~combout {} resultado[15] {} } { 0.000ns 0.000ns 2.254ns } { 0.000ns 0.984ns 0.858ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { rst_i resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "4.096 ns" { rst_i {} rst_i~combout {} resultado[15] {} } { 0.000ns 0.000ns 2.254ns } { 0.000ns 0.984ns 0.858ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Peak virtual memory: 153 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:28:18 2012 " "Info: Processing ended: Tue Aug 14 00:28:18 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}