Subversion Repositories gpib_controller

-- RAMB16_S9_S18: Virtex-II/II-Pro, Spartan-3/3E 2k/1k x 8/16 + 1/2 Parity bits Parity bits Dual-Port RAM
        -- Xilinx HDL Language Template, version 9.1i

        RAMB16_S9_S18_inst : RAMB16_S9_S18
        generic map (
                INIT_A => X"000", --  Value of output RAM registers on Port A at startup
                INIT_B => X"00000", --  Value of output RAM registers on Port B at startup
                SRVAL_A => X"000", --  Port A ouput value upon SSR assertion
                SRVAL_B => X"00000", --  Port B ouput value upon SSR assertion
                WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
                WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
                SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
                -- The following INIT_xx declarations specify the initial contents of the RAM
                -- Port A Address 0 to 511, Port B Address 0 to 255
                INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- Port A Address 512 to 1023, Port B Address 256 to 511
                INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- Port A Address 1024 to 1535, Port B Address 512 to 767
                INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- Port A Address 1536 to 2047, Port B Address 768 to 1024
                INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
                INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- The next set of INITP_xx are for the parity bits
                -- Port A Address 0 to 511, Port B Address 0 to 255
                INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- Port A Address 512 to 1023, Port B Address 256 to 511
                INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- Port A Address 1024 to 1535, Port B Address 512 to 767
                INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
                -- Port A Address 1536 to 2047, Port B Address 768 to 1024
                INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
                INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
        port map (
                DOA => DOA,             -- Port A 8-bit Data Output
                DOB => m_data_out,              -- Port B 16-bit Data Output
                DOPA => DOPA,    -- Port A 1-bit Parity Output
                DOPB => m_parity_out,    -- Port B 2-bit Parity Output
                ADDRA => ADDRA,  -- Port A 11-bit Address Input
                ADDRB => m_addr,  -- Port B 10-bit Address Input
                CLKA => m_clk,   -- Port A Clock
                CLKB => m_clk,   -- Port B Clock
                DIA => DIA,             -- Port A 8-bit Data Input
                DIB => m_data_in,               -- Port B 16-bit Data Input
                DIPA => DIPA,    -- Port A 1-bit parity Input
                DIPB => m_parity_in,     -- Port-B 2-bit parity Input
                ENA => ENA,             -- Port A RAM Enable Input
                ENB => m_en,            -- PortB RAM Enable Input
                SSRA => SSRA,    -- Port A Synchronous Set/Reset Input
                SSRB => m_ssr,   -- Port B Synchronous Set/Reset Input
                WEA => WEA,             -- Port A Write Enable Input
                WEB => m_we              -- Port B Write Enable Input
        );