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<b><font face="Helvetica, Arial"><font color="#BF0000"><font size=+2>Project 
Name: General-Purpose I/O (GPIO) Core</font></font></font></b>
 
<p><u><font size=+1>Description</font></u> 
<p>The GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals.
<p>
<p><u><font size=+1>Features</font></u>
<p>
The following lists the main features of GPIO IP core:
<ul>
<li>Number of general-purpose I/O signals is user selectable and can be in range from 1 to 32. For more I/Os several GPIO cores can be used in parallel.</li>
<li>All general-purpose I/O signals can be bi-directional (external bi-directional I/O cells are required in this case).</li>
<li>All general-purpose I/O signals can be three-stated or open-drain enabled (external three-state or open-drain I/O cells are required in this case).</li>
<li>General-purpose I/O signals programmed as inputs can cause interrupt to the CPU.</li>
<li>General-purpose I/O signals programmed as inputs can be registered at raising edge of system clock or at user programmed edge of external clock.</li>
<li>All general-purpose I/O signals are programmed as inputs at hardware reset.</li>
<li>Auxiliary inputs to GPIO core to bypass outputs from RGPIO_OUT register.</li>
<li>Alternative input reference clock signal from external interface.</li>
<li>WISHBONE SoC Interconnection Rev. B compliant interface</li>
</ul>
<p>More information about the WISHBONE SoC and a full specification can be found 
  <a href="http://www.opencores.org/wishbone/">here</a>. 
<p>For further information, questions and general discussions related to the GPIO 
  core, please visit the <a href="http://www.opencores.org/ml-archive/cores/maillist.shtml">Cores 
  Mailing list.</a> To subscribe to the Cores mailing list go to the <a href="http://www.opencores.org/mailinglists.shtml">Mailing-Lists 
  page</a> and select cores from the pull down menu at the end of the page. Enter 
  your email address and click "Do it!"
<p>   
<p><u><font size=+1>Status</font></u> 
<ul>
  <li>Verilog RTL and verification suite under development</li>
  <li>The Specification is complete: <a href="http://www.opencores.org/cores/gpio/gpio_spec.pdf">gpio_spec.pdf 
    (about 2.3MB)</a></li>
</ul>
<p> </p>
<p><u><font size=+1>Downloading</font></u></p>
<p>To get a snapshot of the latest release, please go to <a href="http://www.opencores.org/cvsmodule.shtml">CVSget</a> 
  (from main OpenCores web page) and enter "gpio" as Module 
  Name (without quotes). This will create a gzip'ed tar file of the entire GPIO 
  core. 
<p>  
<p><u><font size=+1>Author / Maintainer</font></u> 
<p>Damjan Lampret <br>
  <a href="mailto:lampret@opencores.org_NOSPAM">lampret@opencores.org_NOSPAM</a>
<br>
<p>Feel free to send me comments, suggestions and bug reports. 
<p>  
<p><u><font size=+1>Change Log</font></u> 
<ul>
  <li>22/3/2001 DL Preliminary Spec available</li>
  <li>21/3/2001 DL Initial web page </li>
</ul>
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