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<META NAME="GENERATOR" CONTENT="TtH 2.67">
<H3 align=center>Jamil Khatib </H3>
<title> HDLC controller core</title>
<H1 align="center">HDLC controller core </H1>
<p>
<center>(C) Copyright 2001 Jamil Khatib.</center>
<p>
<H1>Contents </H1><A href="#tth_sEc1"
>1 List of authors and changes</A><br>
<A href="#tth_sEc2"
>2 Project Definition</A><br>
<A href="#tth_sEc2.1"
>2.1 Introduction</A><br>
<A href="#tth_sEc2.2"
>2.2 Objectives</A><br>
<A href="#tth_sEc3"
>3 Specifications</A><br>
<A href="#tth_sEc3.1"
>3.1 System Features Specification</A><br>
<A href="#tth_sEc3.2"
>3.2 External Interfaces</A><br>
<A href="#tth_sEc3.2.1"
>3.2.1 Receive Channel</A><br>
<A href="#tth_sEc3.2.2"
>3.2.2 Back-end interface mapping to Wishbone SoC bus</A><br>
<A href="#tth_sEc3.2.3"
>3.2.3 Transmit Channel</A><br>
<A href="#tth_sEc3.2.4"
>3.2.4 Back-end interface mapping to Wishbone SoC bus</A><br>
<A href="#tth_sEc3.2.5"
>3.2.5 CPU interface</A><br>
<A href="#tth_sEc4"
>4 Design description</A><br>
<A href="#tth_sEc4.1"
>4.1 Receive Channel</A><br>
<A href="#tth_sEc4.1.1"
>4.1.1 Design notes</A><br>
<A href="#tth_sEc4.1.2"
>4.1.2 Timing</A><br>
<A href="#tth_sEc4.2"
>4.2 Transmit Channel</A><br>
<A href="#tth_sEc4.2.1"
>4.2.1 Design notes</A><br>
<A href="#tth_sEc4.2.2"
>4.2.2 Timing</A><br>
<A href="#tth_sEc4.3"
>4.3 External FIFO and registers</A><br>
<A href="#tth_sEc4.4"
>4.4 Registers</A><br>
<A href="#tth_sEc4.4.1"
>4.4.1 Transmit</A><br>
<A href="#tth_sEc4.4.2"
>4.4.2 Receive</A><br>
<A href="#tth_sEc4.5"
>4.5 Transmit Frame</A><br>
<A href="#tth_sEc4.6"
>4.6 Receive Frame</A><br>
<A href="#tth_sEc4.7"
>4.7 Connection to TDM controller</A><br>
<A href="#tth_sEc4.8"
>4.8 Clocks Synchronization</A><br>
<A href="#tth_sEc4.9"
>4.9 Diagrams</A><br>
<A href="#tth_sEc5"
>5 Testing and verifications</A><br>
<A href="#tth_sEc5.1"
>5.1 Simulation and Test benches</A><br>
<A href="#tth_sEc5.2"
>5.2 Verification techniques and algorithms</A><br>
<A href="#tth_sEc5.3"
>5.3 Test plans</A><br>
<A href="#tth_sEc6"
>6 Implementations</A><br>
<A href="#tth_sEc6.1"
>6.1 Scripts, files and any other information</A><br>
<A href="#tth_sEc6.2"
>6.2 Design conventions and coding styles</A><br>
<A href="#tth_sEc7"
>7 Reviews and comments</A><br>
<A href="#tth_sEc8"
>8 References</A><br>
<p>
<H2><A NAME="tth_sEc1">
1</A> List of authors and changes</H2>
<p>
<TaBle border>
<tr><td>Name </td><td>Changes </td><td>Date </td><td>Contact address</td></tr><tr><td>
<tr><td>Jamil Khatib </td><td>Initial release </td><td>9-1-2001 </td><td>khatib@ieee.org </td></tr>
<tr><td>Jamil Khatib </td><td>TX interface added, Spec improved </td><td>27-1-2001 </td><td>khatib@ieee.org </td></tr>
<tr><td>Jamil Khatib </td><td>External FIFO buffer added </td><td>3-2-2001 </td><td>khatib@ieee.org </td></tr>
<tr><td>Jamil Khatib </td><td>Registers and CPU interface added </td><td>8-2-2001 </td><td>khatib@ieee.org </td></tr>
<tr><td>Jamil Khatib </td><td>Drop bit, TDM interface are added </td><td>9-2-2001 </td><td>khatib@ieee.org </td></tr>
<tr><td>Jamil Khatib </td><td>More design descriptions added </td><td>2-4-2001 </td><td>khatib@ieee.org </td></tr>
<tr><td>Jamil Khatib </td><td>FIFO buffers calculations added </td><td>9-4-2001 </td><td>khatib@ieee.org </td></tr></TaBle>
<p>
<H2><A NAME="tth_sEc2">
2</A> Project Definition</H2>
<p>
<H3><A NAME="tth_sEc2.1">
2.1</A> Introduction</H3>
HDLC protocol is used as a data link of most of the current communication systems like ISDN, Frame Relay etc. HDLC is a family of protocols that varies in address size, control field, FCS and no. of data bits.
<p>
<H3><A NAME="tth_sEc2.2">
2.2</A> Objectives</H3>
The aim of this project is to develop the basic HDLC functionalities to be used by many communication systems.
<p>
<H2><A NAME="tth_sEc3">
3</A> Specifications</H2>
<p>
<H3><A NAME="tth_sEc3.1">
3.1</A> System Features Specification</H3>
<OL type="1">
<li> Synchronous operation
<li> 8 bit parallel back-end interface
<li> Use external RX and TX clocks
<li> Start and end of frame pattern generation
<li> Start and end of frame pattern checking
<li> Idle pattern generation and detection (all ones)
<li> Zero insertion and removal for transparent transmission.
<li> Abort pattern generation and checking (7 ones)
<li> Address insertion and detection by software
<li> CRC generation and checking (CRC-16 or CRC-32 can be used which is configurale at the code top level)
<li> FIFO buffers and synchronization (External)
<li> Byte aligned data (if data is not aligned to 8-bits error signal is reported to the backend interface)
<li> Q.921, LAPD and LAPB compliant.
<li> The core should not have internal configuration registers or counters, instead it provides all the signals to implement external registers.
<li> There is No limit on the Maximum frame size as long as the backend can read and write data (depends on the external FIFO size)
<li> Bus connection is not supported directly (TxEN and RxEN pins can be used for that reason)
<li> Retransmission is not supported when there is collision in the Bus connection mode.
<li> This controller is used for low speed application only (relative to the backend bus).
<li> Supports connection to TDM core via backend interface and software control for time slot selection and control (signaling ,etc.) generation.
<li> Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.
<li> Optional External FIFO buffers, configuration and status registers.
<li> The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers.
</OL>
<p>
<H3><A NAME="tth_sEc3.2">
3.2</A> External Interfaces</H3>
<p>
<H4><A NAME="tth_sEc3.2.1">
3.2.1</A> Receive Channel</H4>
<p>
<TaBle border>
<tr><td>Signal name</td><td>Direction</td><td>Description</td></tr><tr><td>
<tr><td>Control interface </td><td></td><td></td></tr><tr><td>
<tr><td>Rst </td><td>Input </td><td>System asynchronous reset(active low)</td></tr><tr><td>
<tr><td>Serial Interface </td><td></td><td></td></tr><tr><td>
<tr><td>RxClk </td><td>Input </td><td>Receive Clock</td></tr>
<tr><td>Rx </td><td>Input</td><td>Receive Data</td></tr>
<tr><td>RxEn </td><td>Input </td><td>RX enable (active high)</td></tr><tr><td>
<tr><td>Back-end Interface </td><td></td><td></td></tr><tr><td>
<tr><td>RxD[7:0]</td><td>Output</td><td>Receive data bus</td></tr>
<tr><td>ValidFrame</td><td>Output</td><td>Valid Frame indication during all frame bytes transfer</td></tr>
<tr><td>FrameErr</td><td>Output</td><td>Error in the received data (lost bits)</td></tr>
<tr><td>Aborted</td><td>Output</td><td>Aborted Frame</td></tr>
<tr><td>Read</td><td>Input</td><td>Read byte</td></tr>
<tr><td>Ready</td><td>Output</td><td>Valid data exists</td></tr></TaBle>
<p>
<H4><A NAME="tth_sEc3.2.2">
3.2.2</A> Back-end interface mapping to Wishbone SoC bus</H4>
The HDLC receive backend interface can be used as a slave core or master according to the below mapping. The core supports SINGLE READ Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
<p>
<p><A NAME="tth_fIg1">
</A> <a href="wishlogo.ps">Figure</a><A NAME="Logo">
</A><p>
<TaBle border>
<tr><td>Signal Name</td><td>Wishbone signal</td></tr><tr><td>
<tr><td>Master Configuration connected to FIFO</td><td></td></tr>
<tr><td>RxClk </td><td>CLK_I</td></tr>
<tr><td>Rst </td><td>not RST_I</td></tr>
<tr><td>RxD[7:0]</td><td>DAT_O(7:0)</td></tr>
<tr><td>ValidFrame</td><td>STB_O</td></tr>
<tr><td>ValidFrame</td><td>CYC_O</td></tr>
<tr><td>ReadByte</td><td>ACK_I and not RTY_I</td></tr>
<tr><td>Ready</td><td>WE_O</td></tr>
<tr><td>FrameERR</td><td>TAG0_O</td></tr>
<tr><td>Aborted</td><td>TAG1_O</td></tr>
<tr><td>Slave FIFO(two-clock domain FIFO)</td><td></td></tr>
<tr><td>Data[7:0]</td><td>DAT_I(7:0)</td></tr>
<tr><td>Chip Select</td><td>STB_I</td></tr>
<tr><td>STB_I and not FullFlag</td><td>ACK_O</td></tr>
<tr><td>FullFlag</td><td>RTY_O</td></tr>
<tr><td>Write</td><td>WE_I</td></tr>
<tr><td>Slave Configuration </td><td></td></tr>
<tr><td>RxClk </td><td>CLK_I</td></tr>
<tr><td>Rst </td><td>not RST_I</td></tr>
<tr><td>RxD[7:0]</td><td>DAT_O(7:0)</td></tr>
<tr><td>ValidFrame</td><td>TAG0_O</td></tr>
<tr><td>ReadByte</td><td>not WE_I</td></tr>
<tr><td>Ready</td><td>not RTY_O</td></tr>
<tr><td>STB_I and not WR_I</td><td>ACK_O</td></tr>
<tr><td>FrameERR</td><td>TAG1_O</td></tr>
<tr><td>Aborted</td><td>TAG2_O</td></tr></TaBle>
<p>
<H4><A NAME="tth_sEc3.2.3">
3.2.3</A> Transmit Channel</H4>
<TaBle border>
<tr><td>Signal name</td><td>Direction</td><td>Description</td></tr><tr><td>
<tr><td>Control interface </td><td></td><td></td></tr><tr><td>
<tr><td>Rst </td><td>Input </td><td>System asynchronous reset(active low)</td></tr><tr><td>
<tr><td>Serial Interface </td><td></td><td></td></tr><tr><td>
<tr><td>TxClk </td><td>Input </td><td>Transmit Clock</td></tr>
<tr><td>Tx </td><td>Output </td><td>Transmit Data</td></tr>
<tr><td>TxEn </td><td>Input </td><td>TX enable (active high)</td></tr><tr><td>
<tr><td>Back-end Interface </td><td></td><td></td></tr><tr><td>
<tr><td>TxD[7:0]</td><td>Input </td><td>Transmit data bus</td></tr>
<tr><td>ValidFrame</td><td>Input</td><td>Valid Frame indication during all frame bytes transfer</td></tr>
<tr><td>AbortedTrans</td><td>Output</td><td>Error in the transmitted data (Abort pattern was generated)</td></tr>
<tr><td>AbortFrame</td><td>Input</td><td>Abort Frame</td></tr>
<tr><td>Write</td><td>Input</td><td>Write byte</td></tr>
<tr><td>Ready</td><td>Output</td><td>Can accept new data</td></tr></TaBle>
<p>
<H4><A NAME="tth_sEc3.2.4">
3.2.4</A> Back-end interface mapping to Wishbone SoC bus</H4>
The HDLC receive backend interface can be used as a slave core or master according to the below mapping. The core supports SINGLE WRITE Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
<p>
<TaBle border>
<tr><td>Signal Name</td><td>Wishbone signal</td></tr><tr><td>
<tr><td>Master Configuration connected to FIFO</td><td></td></tr>
<tr><td>TxClk </td><td>CLK_I</td></tr>
<tr><td>Rst </td><td>not RST_I</td></tr>
<tr><td>TxD[7:0]</td><td>DAT_I(7:0)</td></tr>
<tr><td>Write</td><td>ACK_I and not RTY_I</td></tr>
<tr><td>Ready</td><td>not WE_O</td></tr>
<tr><td>AbortedTrans</td><td>TAG0_O</td></tr>
<tr><td>ValidFrame</td><td>TAG1_I</td></tr>
<tr><td>AbortFrame</td><td>TAG0_I</td></tr>
<tr><td>Always Active </td><td>CYC_O</td></tr>
<tr><td>Always Active </td><td>STB_O</td></tr>
<tr><td>Slave FIFO(two-clock domain FIFO)</td><td></td></tr>
<tr><td>Data[7:0]</td><td>DAT_I(7:0)</td></tr>
<tr><td>EmptyFlag</td><td>RTY_O</td></tr>
<tr><td>Read</td><td>WE_I</td></tr>
<tr><td>WE_I and not EmptyFlag</td><td>ACK_O</td></tr>
<tr><td>ChipSelect</td><td>STB_I</td></tr>
<tr><td>Slave Configuration </td><td></td></tr>
<tr><td>TxClk </td><td>CLK_I</td></tr>
<tr><td>Rst </td><td>not RST_I</td></tr>
<tr><td>TxD[7:0]</td><td>DAT_I(7:0)</td></tr>
<tr><td>ValidFrame</td><td>STB_I</td></tr>
<tr><td>Write</td><td>WE_I</td></tr>
<tr><td>Ready</td><td>not RTY_O</td></tr>
<tr><td>STB_I and WR_I</td><td>ACK_O</td></tr>
<tr><td>AbortFrame</td><td>TAG0_I</td></tr>
<tr><td>AbortedTrans</td><td>TAG0_O</td></tr></TaBle>
<p>
<H4><A NAME="tth_sEc3.2.5">
3.2.5</A> CPU interface</H4>
This interface is used when the FIFO and registers are included in the Core. This interface is compatible to WishBone slave bus interface that supports single read/write cycles and block cycles. The interface supports the following wishbone signals.
<p>
<TaBle border>
<tr><td>Signal</td><td>Note</td></tr><tr><td>
<tr><td>RST_I</td><td>Reset</td></tr>
<tr><td>CLK_I</td><td>Clock</td></tr>
<tr><td>ADR_I(2:0)</td><td>3-bit address line</td></tr>
<tr><td>DAT_O(7:0)</td><td>8-bit receive data</td></tr>
<tr><td>DAT_I(7:0)</td><td>8-bit transmit data</td></tr>
<tr><td>WE_I</td><td>Read/write</td></tr>
<tr><td>STB_I</td><td>Strobe</td></tr>
<tr><td>ACK_O</td><td>Acknowledge</td></tr>
<tr><td>CYC_I</td><td>Cycle</td></tr>
<tr><td>TAG0_O</td><td>TxDone interrupt</td></tr>
<tr><td>TAG1_O</td><td>RxReady interrupt</td></tr></TaBle>
<p>
<H2><A NAME="tth_sEc4">
4</A> Design description</H2>
<p>
<H3><A NAME="tth_sEc4.1">
4.1</A> Receive Channel</H3>
<p>
<H4><A NAME="tth_sEc4.1.1">
4.1.1</A> Design notes</H4>
<p>
Receive channel provides interface to the backend via a simple handshake protocol that can be used to connect the controller to either a shared memory or FIFO buffer. This protocol uses the hand shack protocol of the Wishbone SoC bus.
<p>
Receive channel supports only 8-bits aligned data. Each frame starts with a starting flag (01111110) and ends with starting flag (01111110). Since the receipt ion is synchronous only, the channel uses the external clock and a byte must be read from the channel within the first 7 clock pulses after the ready signal is asserted. If no data is read during this period (while ValidFrame signal is active) FrameErr is signaled reported to the backend as long the ValidFrame is active. FrameErr is signaled also when non 8-bit aligned data is received and when FCS error is found.
<p>
<H4><A NAME="tth_sEc4.1.2">
4.1.2</A> Timing</H4>
<p>
<H3><A NAME="tth_sEc4.2">
4.2</A> Transmit Channel</H3>
Transmit channel provides interface to the backend via a simple handshake protocol that can be used to connect the controller to either a shared memory or FIFO buffer. This protocol uses the handshack protocol of the Wishbone SoC bus.
<p>
Transmit channel supports only 8-bits aligned data. Each frame starts with a starting flag (01111110) and ends with starting flag (01111110). Since the transmission is synchronous only, the channel uses the external clock and a byte must be written to the channel within the first 7 clock pulses after the ready signal is asserted. If no data is inserted during this period (while ValidFrame signal is active) abort pattern is transmitted and reported to the backend via AboredTrans signal as long the ValidFrame is active.
<p>
<H4><A NAME="tth_sEc4.2.1">
4.2.1</A> Design notes</H4>
<p>
<H4><A NAME="tth_sEc4.2.2">
4.2.2</A> Timing</H4>
The channel starts accepting data after asserting the ValidFrame signal. This signal can control no of idle pattern bits (e.g. if this signal is de-asserted for 8 bits only a single Idle pattern (8 ones) is inserted). Valid Frame signal must be asserted for 8 clocks after any valid write operation.
<p>
<H3><A NAME="tth_sEc4.3">
4.3</A> External FIFO and registers</H3>
The controller has optional external FIFO buffers, one for data to be transmitted and one for data to be received. Status and control registers are available to control these FIFOs. These two blocks (FIFOs and registers) are built around the HDLC controller core which make them optional if the core is to be used in different kind of applications.
The current implementation supports the following configuration:
The size of the Transmit and receive FIFOs is (8×128) bits which enables 128 maximum HDLC frame size.
<p>
The transmit buffer is used to prevent underflow while transmitting bytes to the line. All bytes will be available once the transmit is enabled. The Receive buffer is used to provide data burst transfer to the Back end interface which prevents the back end from reading each byte alone. The FIFO size is suitable for operating frequencies 2.048MHz on the serial interface and 50 MHz on the back end interface. Other frequencies can operate if the delay between HDLC frames is less than the delay needed for the back end to empty the internal FIFO (the next calculations is an example to be applied for different frequencies)
<p>
7 bits (minimum bits between HDLC Frames) / 2.048MHz = 3.418 us
<p>
128 Bytes (Maximum frame size) / 50MHz = 2.56 us
<p>
These FIFOs are implemented on Single port memory. Two interrupt lines are used, one to signal transmission done and one to request transfer of received frame to memory. These interrupts are also reflected in Status registers to support polling mode for the controller.
<p>
<H3><A NAME="tth_sEc4.4">
4.4</A> Registers</H3>
All internal registers are 8-bit width.
<H4><A NAME="tth_sEc4.4.1">
4.4.1</A> Transmit</H4>
<p>
<TaBle>
<tr><td><b>Tx Status and Control Register: Tx_SC</b> </td><td>Offset Address = 0x0</td></tr></TaBle>
<br>
<p>
<TaBle border><tr><td>
<tr><td>BIT </td><td align="center">7 </td><td align="center">6 </td><td align="center">5 </td><td align="center">4 </td><td align="center">3 </td><td align="center">2 </td><td align="center">1 </td><td align="center">0</td></tr>
<tr><td>FIELD </td><td align="center">N/A </td><td align="center">N/A </td><td align="center">FCSen </td><td align="center">FIFOOverflow</td><td align="center">Aborted</td><td align="center">TxAbort</td><td align="center">TxEnable</td><td align="center">TxDone</td></tr>
<tr><td>RESET </td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td></tr>
<tr><td>R/W </td><td align="center">RO</td><td align="center">RO</td><td align="center">WO</td><td align="center">RO</td><td align="center">RO</td><td align="center">WO</td><td align="center">WO</td><td align="center">RO</td></tr></TaBle>
<br>
<p>
<TaBle>
<tr><td><b>Tx FIFO buffer register: Tx_Buffer</b> </td><td>Offset Address = 0x1</td></tr></TaBle>
<br>
<p>
<TaBle border><tr><td>
<tr><td>BIT </td><td align="center">7-0</td></tr>
<tr><td>FIELD </td><td align="center">Transmit Data byte</td></tr>
<tr><td>RESET </td><td align="center">0x0</td></tr>
<tr><td>R/W </td><td align="center">WO</td></tr></TaBle>
<p>
<H4><A NAME="tth_sEc4.4.2">
4.4.2</A> Receive</H4>
<p>
<TaBle>
<tr><td><b>Rx Status and Control Register: Rx_SC</b> </td><td>Offset Address = 0x2</td></tr></TaBle>
<br>
<p>
<TaBle border><tr><td>
<tr><td>BIT </td><td align="center">7 </td><td align="center">6 </td><td align="center">5 </td><td align="center">4 </td><td align="center">3 </td><td align="center">2 </td><td align="center">1 </td><td align="center">0</td></tr>
<tr><td>FIELD </td><td align="center">N/A </td><td align="center">N/A </td><td align="center">N/A </td><td align="center">FIFOOverflow</td><td align="center">Aborted</td><td align="center">FrameError</td><td align="center">Drop</td><td align="center">RxReady</td></tr>
<tr><td>RESET </td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td><td align="center">0</td></tr>
<tr><td>R/W </td><td align="center">RO</td><td align="center">RO</td><td align="center">RO</td><td align="center">RO</td><td align="center">RO</td><td align="center">RO</td><td align="center">WO</td><td align="center">RO</td></tr></TaBle>
<br>
<p>
<TaBle>
<tr><td><b>Rx FIFO buffer register: Rx_Buffer</b> </td><td>Offset Address = 0x3</td></tr></TaBle>
<br>
<p>
<TaBle border><tr><td>
<tr><td>BIT </td><td align="center">7-0</td></tr>
<tr><td>FIELD </td><td align="center">Received Data byte</td></tr>
<tr><td>RESET </td><td align="center">0x0</td></tr>
<tr><td>R/W </td><td align="center">RO</td></tr></TaBle>
<br>
<p>
<TaBle>
<tr><td><b>Rx Frame length: Rx_Len</b> </td><td>Offset Address = 0x4</td></tr></TaBle>
<br>
<p>
<TaBle border><tr><td>
<tr><td>BIT </td><td align="center">7-0</td></tr>
<tr><td>FIELD </td><td align="center">Frame Length</td></tr>
<tr><td>RESET </td><td align="center">0x0</td></tr>
<tr><td>R/W </td><td align="center">RO</td></tr></TaBle>
<br>
<p>
<H3><A NAME="tth_sEc4.5">
4.5</A> Transmit Frame</H3>
<UL>
<li> The CPU should check TxDone (in Tx status register 0x0) bit of it is '1' or wait for TxDone interrupt. TxDone bit is reset to '0' after the first write to Tx FIFO Buffer register (0x1).
<li> The CPU should write frame data bytes to Tx FIFO buffer register (0x1).
<li> After writing all data bytes to TX buffer register, the CPU should write '1' to TxEnable to enable data transmission to the line. After writing to this bit no further write operation to Tx FIFO buffer register is allowed till TxDone is set (all writes will be ignored).
<li> It is optional for the CPU to check the status bits of Tx status register.
</UL>
<p>
<H3><A NAME="tth_sEc4.6">
4.6</A> Receive Frame</H3>
<UL>
<li> The controller sets RxReady bit in Rx Status and control register (0x2) and sets the TxReady interrupt line to indicate valid frame in internal buffer is available.
<li> It is recommended that the CPU read the Rx Status and control register (0x3).
<li> The CPU should read the Frame length register (0x4) to check the size of the frame. The value of this regiter is valid only after the RxReady bit is set and remains valid till the first read from the Data buffer.
<li> The CPU should read Rx FIFO buffer register (0x3) Frame length times to get all frame bytes. Performing extra reads (read from empty buffer) produces invalid data.
<li> If the CPU does not read all frame bytes as soon as possible the internal buffer will overflow and FIFOOverflow bit will be set and the current frame should be dropped. No further read operations should be attempted till RxReady bit is set again and RxReady interrupt is signaled indicating new available frame.
<li> The software can drop entire frame from the Receive FIFO buffer by writing 1 to drop bit in the status and control receive register (0x3). This is suitable for dropping bad frames (for any reason) or frames with incorrect addresses.
</UL>
<p>
<H3><A NAME="tth_sEc4.7">
4.7</A> Connection to TDM controller</H3>
This controller can get/send data from/to TDM controller through software control. The software configures the TDM controller to select the channel. It adds/removes the address and control information fields of the HDLC frame. Then passes the data field between the two controllers through optional DMA transfer.
<p>
<H3><A NAME="tth_sEc4.8">
4.8</A> Clocks Synchronization</H3>
Since the core can operate in different clock domains (The serial line domain and the backend interface domain), all control signals pass through two flip flops to reduce the metastability. These Flip Flops are clocked with the same clock of the interface that read these signals.
<p>
<H3><A NAME="tth_sEc4.9">
4.9</A> Diagrams</H3>
<p><A NAME="tth_fIg1">
</A>
<a href="HDLC_top.ps">Figure</a>
<center>Figure 1: HDLC core</center><A NAME="Core">
</A>
<p>
<p>
<p><A NAME="tth_fIg2">
</A> <a href="HDLC_cont.ps">Figure</a> <center>Figure 2: HDLC controller</center><A NAME="controller">
</A>
<p>
<p>
<H2><A NAME="tth_sEc5">
5</A> Testing and verifications</H2>
<p>
<TaBle border>
<tr><td>Requirement </td><td>Test method </td><td>Validation method </td></tr><tr><td>
<tr><td>Interface timing </td><td></td><td></td></tr>
<tr><td></td><td></td><td></td></tr><tr><td>
<tr><td>Functionality </td><td></td><td></td></tr></TaBle>
<H3><A NAME="tth_sEc5.1">
5.1</A> Simulation and Test benches</H3>
<p>
<H3><A NAME="tth_sEc5.2">
5.2</A> Verification techniques and algorithms</H3>
<p>
<H3><A NAME="tth_sEc5.3">
5.3</A> Test plans</H3>
<p>
<H2><A NAME="tth_sEc6">
6</A> Implementations</H2>
The design is implemented using the VHDL language. The design is divided into three main blocks, serial Receive channel, Serial Transmit channel and the Top blocks.
The Receive and Transmit serial channels perform the HDLC
functionality. The Top blocks perform the FCS calculation (Which is
either FCS-16 or FCS-32), the frame buffering the interface with the
back end system and the synchronization between the clocks. The FCS and Buffering can be changed by replacing the corresponding files.
<p>
<H3><A NAME="tth_sEc6.1">
6.1</A> Scripts, files and any other information</H3>
<TaBle border>
<tr><td>RX </td><td></td></tr>
<tr><td>RxChannel.vhd </td><td>Top Rx Channel </td></tr>
<tr><td>Rxcont.vhd </td><td>Rx Controller </td></tr>
<tr><td>Zero_detect.vhd </td><td>Zero detect and serial to parallel </td></tr>
<tr><td>flag_detect.vhd </td><td>Flag detection </td></tr>
<tr><td>TX </td><td></td></tr>
<tr><td>TxChannel.vhd </td><td>Top Tx channel </td></tr>
<tr><td>TXcont.vhd </td><td>Tx Controller</td></tr>
<tr><td>zero_ins.vhd </td><td>Zero insertion and parallel to serial </td></tr>
<tr><td>flag_ins.vhd </td><td>Flag insertion </td></tr>
<tr><td>Top </td><td></td></tr>
<tr><td>TxBuff.vhd</td><td>Tx buffer</td></tr>
<tr><td>TxFCS.vhd </td><td>Tx FCS-16</td></tr>
<tr><td>TxSync.vhd </td><td>Tx synchronization</td></tr>
<tr><td>RxBuff.vhd</td><td>Rx buffer</td></tr>
<tr><td>RxFCS.vhd </td><td>Rx FCS-16</td></tr>
<tr><td>RxSync.vhd </td><td>Rx synchronization</td></tr>
<tr><td>WB_IF.vhd </td><td>WishBone interface</td></tr>
<tr><td>hdlc.vhd </td><td>Top HDLC controller</td></tr></TaBle>
<p>
<H3><A NAME="tth_sEc6.2">
6.2</A> Design conventions and coding styles</H3>
<p>
<H2><A NAME="tth_sEc7">
7</A> Reviews and comments</H2>
<p>
<H2><A NAME="tth_sEc8">
8</A> References</H2>
<p>
<p><hr><small>File translated from
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