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<!--# set var="title" value="" --> <!--# include virtual="/ssi/ssi_start.shtml" --> <p><font size=+2 face="Helvetica, Arial" color=#bf0000><b>HDLC controller</font></b><h3>Introduction</h3><h3>HDLC controller features</h3><ul><li>1. 8 bit parallel backend interface<li>2. use external RX and TX clocks<li>3. Start and end of frame pattern generation<li>4. Start and end of frame pattern checking<li>5. Idle pattern generation and detection (all ones)<li>5. a) Idle pattern is assumed only after the end of a frame which is signaled by an abort signal<li>6. Zero insertion <li>7. Abort pattern generation and checking<li>8. Address insertion and detection by software<li>9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)<li>10. FIFO buffers and synchronization (External)<li>11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)<li>12. Q.921, LAPB and LAPD compliant.<li>13. For complete specifications refer to spec document</ul><h3>System specifications and interfaces</h3><a href="hdlc_project.html">Check the system spec and interaces</a> or you can download the <a href="hdlc_project.ps">PS file</a> or <a href="hdlc_project.pdf">PDF file</a><h3>Core top block diagram</h3><center><img src="HDLC_top.jpg"></center> <h3>Status</h3>The VHDL code is ready in the opencores CVS. The code needs verification contact me if you are intrested in helping me. <ul> <li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/hdlc/code"> download code </a> <li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/memory_cores2"> download memory module needed for buffers </a> <li><a href="http://www.opencores.org/cgi-bin/cvsget.cgi/hdlc"> download the whole module</a> </ul> <h3>Resource usage</h3> <br> <b>Rx Channel Block</b>: which includes HDLC Framing extraction, zero removal and conversion from serial to parallel. <table BORDER COLS=7 WIDTH="100%" > <tr> <td><b>Vendor</b></td> <td><b>Device</b></td> <td><b>Size</b></td> <td><b>Frequency </b></td> <td><b>Board Tested</b></td> <td><b>Functional Test</b></td> <td><b>Notes</b></td> </tr> <tr> <td>Altera</td> <td>EP20K100BC356-3</td> <td>108 LCs</td> <td>91.48MHz</td> <td>-</td> <td>-</td> <td>No optimization was peroformed, using Quartus II</td> </tr> <tr> <td><!--Altera--></td> <td><!--EP1K30TC144-3--></td> <td><!--114 LCs --></td> <td><!--43.6 MHz--></td> <td></td> <td></td> <td><!--No optimization was peroformed--></td> </tr> <tr> <td><!--Altera--></td> <td><!--EPM7128AELC84-12--></td> <td><!--83 LCs--></td> <td><!--71.4 MHz--></td> <td></td> <td></td> <td><!--No optimization was peroformed--></td> </tr> </table> <br> <!---> <!--> <b>Tx Channel Block</b>: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial. <table BORDER COLS=7 WIDTH="100%" > <tr> <td><b>Vendor</b></td> <td><b>Device</b></td> <td><b>Size</b></td> <td><b>Frequency </b></td> <td><b>Board Tested</b></td> <td><b>Functional Test</b></td> <td><b>Notes</b></td> </tr> <tr> <td>Altera</td> <td>EP20K100BC356-3</td> <td>100 LCs</td> <td>112.42MHz</td> <td>-</td> <td>-</td> <td>No optimization was peroformed, using Quartus II </td> </tr> <tr> <td><!--Altera--></td> <td><!--EP1K30TC144-3--></td> <td><!--114 LCs--></td> <td><!--43.6 MHz--></td> <td></td> <td></td> <td><!--No optimization was peroformed--></td> </tr> <tr> <td><!--Altera--></td> <td><!--EPM7128AELC84-12--></td> <td><!--83 LCs--></td> <td><!--71.4 MHz--></td> <td></td> <td></td> <td><!--No optimization was peroformed--></td> </tr> </table> <!-----------------------------> <br> <b>HDLC controller Block</b>: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers. <table BORDER COLS=7 WIDTH="100%" > <tr> <td><b>Vendor</b></td> <td><b>Device</b></td> <td><b>Size</b></td> <td><b>Frequencies (MHz)</b></td> <td><b>Board Tested</b></td> <td><b>Functional Test</b></td> <td><b>Notes</b></td> </tr> <tr> <td>Altera</td> <td>EP20K100BC356-3</td> <td>630 LCs, 2 ESBs</td> <td>CLK_I=74.02,RxClk=101.86,TxClk=106.42</td> <td>-</td> <td>-</td> <td>No optimization was peroformed, using Quartus II</td> </tr> <tr> <td><!--Altera--></td> <td><!--EP1K30TC144-3--></td> <td><!--114 LCs--></td> <td><!--43.6 MHz--></td> <td></td> <td></td> <td><!--No optimization was peroformed--></td> </tr> <tr> <td><!--Altera--></td> <td><!--EPM7128AELC84-12--></td> <td><!--83 LCs--></td> <td><!--71.4 MHz--></td> <td></td> <td></td> <td><!--No optimization was peroformed--></td> </tr> </table> <!----------------------------> <h3>Links</h3> <ul> <li><a href="http://www.rad.com/networks/1994/hdlc/hdlc.htm">http://www.rad.com/networks/1994/hdlc/hdlc.htm</a> <li><a href="http://www.erg.abdn.ac.uk/users/gorry/course/dl-pages/hdlc-framing.html">http://www.erg.abdn.ac.uk/users/gorry/course/dl-pages/hdlc-framing.html</a> <li><a href="http://members.tripod.com/~vkalra/hdlc.html">http://members.tripod.com/~vkalra/hdlc.html</a> <li><a href="http://goanna.cs.rmit.edu.au/~ivan/cs361/lec/lec5.pdf">http://goanna.cs.rmit.edu.au/~ivan/cs361/lec/lec5.pdf</a> <li><a href="http://www.inicore.com/____pdf/inihdlc.pdf">http://www.inicore.com/____pdf/inihdlc.pdf</a> <li><a href="http://www.mentorg.com/inventra/netlist_program/actel/ds/hdlccoreA1_pd.pdf">http://www.mentorg.com/inventra/netlist_program/actel/ds/hdlccoreA1_pd.pdf</a> </ul> </ul><p>Maintainer(s):<ul>Jamil Khatib</ul><p>Author(s):<ul>Jamil Khatib</ul><p>Contact email:<ul><a href=mailto:khatib@opencores.org_NOSPAM>Khatib@opencores.org_NOSPAM</a></ul><p>Mailing-List:<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</a></ul><!--# include virtual="/ssi/ssi_end.shtml" -->