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<!--# set var="title" value="I2C Master Core" -->
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<b><font size=+2 face="Helvetica, Arial"
color=#bf0000>Project Name: I2C controller core</font></b>
<font size=+1><b>Description</b></font>
I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.
You can find I2C specification on <A HREF=> Phillips web Site</A>.
Work was originally started by Frédéric Renet. You can find his webpage <A href=>here</A>.
<font size=+1><b>What you get</b></font><p>
<li>WISHBONE rev.B2 compliant core
<li>No Multimaster operation
<li>No FIFO
<li>No slave mode
<li>Simple command based interface
<p><font size=+1><b>Documentation</b></font><p>
<li>Revision 0.4 of the WISHBONE I2C Master Core is available <A href=>here</A>.
<p><font size=+1><b>Current status</b></font><p>
<li>Design is available in VHDL and Verilog from OpenCores CVS via <a href="">cvsweb</a> or via <a href="/cvsmodule.shtml">cvsget</a></li>
<li>Note that the Verilog version is currently up-to-date. The VHDL version needs some modifications.</li>
<font size=+1><b>Maintainer(s):</b></font><p>
<p><ul><a>Richard Herveille</A></ul>
<p><font size=+1><b>Mailing-list:</b></font><p>
<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
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