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<b><font size=+2 face="Helvetica, Arial"
color=#bf0000>Project Name: I2C controller core</font></b>
<font size=+1><b>Description</b></font>
I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.
You can find I2C specification on <A HREF=> Phillips web Site</A>.
<font size=+1><b>What you get</b></font><p>
The simplest master I2C ever built! Requirement is low gate count so features are restricted:<BR>
<LI>No Multimaster operation
<LI>No slave mode
The processor interface is composed of four registers:
<LI>Timing Register (TR)
<LI>Control Register (CR)
<LI>Status Register (SR)
<LI>Data Register (DR)
This is a copy of <I>ColdFire</I> MBUS Interface Programmer's Model from Motorola.
There is the preliminary block diagram :
<img src="Block.gif" border="0" ><br>
The design is fully synchronous, only one clock. The Timing register fix the output rate of the I2C bus.
The bus interface is not specified at this time and it would be either OR1K specific bus or APB (from AMBA specification).
Current Status:
working on functional and design specifications
<ul><a href=mailto:f.renet@mipsys.com_NOSPAM>Frédéric Renet</A></ul>
<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>
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