Subversion Repositories jtag

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<b><font size=+2 face="Helvetica, Arial" color=#bf0000>Project Name: IEEE 1149.1 Test Access Port (TAP)</font></b>
<p>
<font size=+1><b>Description</b></font>
 
<p>This implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant. It includes a TAP controller, a 4-bit instruction 
register and three test data registers: idcode register, bypass register and boundary scan register. Boundary scan register is connected to eight
pins (2 inputs, 2 outputs, 2 tristatable outputs and 2 bidirectional pins). Besides the Verilog code, a BSDL file is also provided. The number of
pins can be easily increased by following the instructions. The design had been tested with the JTAG Technologies testing equipment (The TAP controller was implemented in
Xilinx 95144XL). The design will be expanded in the future to support additional instruction and debug capabilities.
<p>
 
Current Status:
<ul>
<li><a href="Boundary-Scan%20Architecture.pdf">A description of a Boundary Scan Implementation(57KB)</a> is avaliable in Adobe PDF format.</li>
<li>Verilog and BSDL files can be accessed via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb.</a></li>
<li>Some additional information can be found <a href="http://www.opencores.org/cores/DebugInterface/">here.</a></li>
</ul>
<p>
Next Step:
<ul>
<li>Implementing additional instructions.</li>
<li><a href="http://www.opencores.org/cores/DebugInterface/">JTAG debug interface for the OR1k processor.</a></li>
</ul>
<p>
Author(s):
<ul><a href="mailto:igorm@opencores.org_NOSPAM">Igor Mohor</a></ul>
<p>Mailing-list:
<ul><a href=mailto:openrisc@opencores.org_NOSPAM>openrisc@opencores.org_NOSPAM</ul>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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