Subversion Repositories lateq

-------------------------------------------------------------------------------
-- Title      : Multiinput comparator for finding of maximum element
-- Project    : 
-------------------------------------------------------------------------------
-- File       : max_finder_1st.vhd
-- Author     : Wojciech M. Zabolotny ( wzab01<at>gmail.com )
-- Company    :
-- License    : BSD
-- Created    : 2013-11-01
-- Last update: 2015-09-24
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2014 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2013-11-01  1.0      WZab    Created
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
use IEEE.NUMERIC_STD.all;
library work;
use work.lateq_pkg.all;
use work.ex1_pkg.all;
use work.ex1_trees_pkg.all;
 
 
entity max_finder_1st is
  port (
    dins  : in  T_EX1_CMP_INS;
    dout  : out T_SINGLE_DATA_WITH_POS;
    clk   : in  std_logic;
    rst_p : in  std_logic);
end max_finder_1st;
 
architecture beh of max_finder_1st is
 
begin
 
  --assert false report "This is report from device:" & desc severity note;
  process (clk, rst_p) is
    variable res       : T_SINGLE_DATA_WITH_POS;
    variable first     : boolean;
    -- pragma translate_off
    variable lateq_mrk : T_LATEQ_MRK;
  -- pragma translate_on 
  begin  -- process
    if clk'event and clk = '1' then     -- rising clock edge
      if rst_p = '1' then               -- asynchronous reset (active high)
        dout <= C_SINGLE_DATA_WITH_POS_INIT;
      else
        first := true;
        res   := C_SINGLE_DATA_WITH_POS_INIT;
        for i in 0 to EX1_NOF_INS_IN_CMP-1 loop
          if dins(i).valid then
            -- In simulation check delays the adjustment blocks should equalize
            -- time marks. So any time marker difference is a sign of serious problem!
            if first then
              res   := dins(i);
              first := false;
            else
              -- pragma translate_off
              -- Check only valid inputs
              assert res.lateq_mrk = dins(i).lateq_mrk report "in entity:" & max_finder_1st'instance_name &
                " different delays between input 0 and input " &
                integer'image(i) & ": " & integer'image(res.lateq_mrk) & "<>" & integer'image(dins(i).lateq_mrk)
                severity failure;
              -- pragma translate_on
              if dins(i).valid and (ex1_cmp_data(dins(i), res) > 0) then
                --report "swapped:" & integer'image(dins(i).value) & "<>" & integer'image(res.value) severity note;
                res := dins(i);
              end if;
            end if;
          end if;
        end loop;  -- i
        --report "dout:" & integer'image(res.value) severity note;
        dout <= res;
      end if;
    end if;
  end process;
 
end beh;