Subversion Repositories lateq

-------------------------------------------------------------------------------
-- Title      : Multiinput adder for creating hierachical adders
-- Project    : 
-------------------------------------------------------------------------------
-- File       : max_finder_1st.vhd
-- Author     : Wojciech M. Zabolotny ( wzab01<at>gmail.com )
-- Company    :
-- License    : BSD
-- Created    : 2013-11-01
-- Last update: 2015-09-24
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2014 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2013-11-01  1.0      WZab    Created
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
use IEEE.NUMERIC_STD.all;
library work;
use work.lateq_pkg.all;
use work.ex1_pkg.all;
use work.ex1_trees_pkg.all;
 
entity tree_adder_1st is
  port (
    dins  : in  T_EX1_ADD_INS;
    dout  : out T_CALC_DATA_MRK;
    clk   : in  std_logic;
    rst_p : in  std_logic);
end tree_adder_1st;
 
architecture beh of tree_adder_1st is
 
begin
 
  process (clk, rst_p) is
    variable res     : T_CALC_DATA_MRK;
    -- pragma translate_off
    variable lateq_mrk : T_LATEQ_MRK;
  -- pragma translate_on
    variable first : boolean := true;
    variable ifirst : integer;
  begin  -- process
    if clk'event and clk = '1' then     -- rising clock edge
      if rst_p = '1' then               -- asynchronous reset (active low)
        dout <= C_CALC_DATA_MRK_INIT;
      else
        first := true;
        res := C_CALC_DATA_MRK_INIT;
        for i in 0 to EX1_NOF_INS_IN_ADD-1 loop
          -- Use only valid inputs
          if dins(i).valid  then
            if first then
              res := dins(i);
              first := false;
              ifirst := i;
            else
              -- pragma translate_off
              assert res.lateq_mrk = dins(i).lateq_mrk report "in entity:" & tree_adder_1st'instance_name &
                "Different delays between input " & integer'image(ifirst) & " and input " &
                integer'image(i) & ": " & integer'image(res.lateq_mrk) & "<>" & integer'image(dins(i).lateq_mrk)
                severity failure;
              -- pragma translate_on
              res.sum := res.sum + dins(i).sum;
            end if;
          end if;
        end loop;  -- i
        dout <= res;
      end if;
    end if;
  end process;
 
end beh;