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<center><font size=+3><b>OPENCORES.ORG</b></font>
<br><font size=-4><font color=#ffffff>.</font></font>
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<font SIZE="2">-- VHDL structural description generated from `counter`
<p>-- date : Tue Feb 20 14:23:43 2001</p>
<p> </p>
<p>-- Entity Declaration</p>
<p>ENTITY counter IS</p>
<p>PORT (</p>
<p>e : in BIT; -- e</p>
<p>ck : in BIT; -- ck</p>
<p>res : in BIT; -- res</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT; -- vss</p>
<p>a : out BIT_VECTOR (0 TO 4); -- a</p>
<p>q_c : out BIT -- q_c</p>
<p>);</p>
<p>END counter;</p>
<p>-- Architecture Declaration</p>
<p>ARCHITECTURE VST OF counter IS</p>
<p>COMPONENT a2_y</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>t : out BIT; -- t</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT xr2_y</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>t : out BIT; -- t</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT dffres</p>
<p>port (</p>
<p>input : in BIT; -- input</p>
<p>ck : in BIT; -- ck</p>
<p>reset : in BIT; -- reset</p>
<p>output : out BIT; -- output</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>SIGNAL c_1 : BIT; -- c_1</p>
<p>SIGNAL c_2 : BIT; -- c_2</p>
<p>SIGNAL c_3 : BIT; -- c_3</p>
<p>SIGNAL d_1 : BIT; -- d_1</p>
<p>SIGNAL d_2 : BIT; -- d_2</p>
<p>SIGNAL d_3 : BIT; -- d_3</p>
<p>SIGNAL d_4 : BIT; -- d_4</p>
<p>BEGIN</p>
<p>an00 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c_1,</p>
<p>i1 => a(0),</p>
<p>i0 => e);</p>
<p>an01 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c_2,</p>
<p>i1 => a(1),</p>
<p>i0 => c_1);</p>
<p>an02 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c_3,</p>
<p>i1 => a(2),</p>
<p>i0 => c_2);</p>
<p>an03 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => q_c,</p>
<p>i1 => a(3),</p>
<p>i0 => c_3);</p>
<p>xr00 : xr2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => d_1,</p>
<p>i1 => a(0),</p>
<p>i0 => e);</p>
<p>xr01 : xr2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => d_2,</p>
<p>i1 => a(1),</p>
<p>i0 => c_1);</p>
<p>xr02 : xr2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => d_3,</p>
<p>i1 => a(2),</p>
<p>i0 => c_2);</p>
<p>xr03 : xr2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => d_4,</p>
<p>i1 => a(3),</p>
<p>i0 => c_3);</p>
<p>dff0 : dffres</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>output => a(0),</p>
<p>reset => res,</p>
<p>ck => ck,</p>
<p>input => d_1);</p>
<p>dff1 : dffres</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>output => a(1),</p>
<p>reset => res,</p>
<p>ck => ck,</p>
<p>input => d_2);</p>
<p>dff2 : dffres</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>output => a(3),</p>
<p>reset => res,</p>
<p>ck => ck,</p>
<p>input => d_3);</p>
<p>dff3 : dffres</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>output => a(4),</p>
<p>reset => res,</p>
<p>ck => ck,</p>
<p>input => d_4);</p>
<p>end VST;</p>
</font>
<b><font size=+1>Maintainers and Authors :</font></b>
<p>LCD Driver development team
<p>current members:
<ul>
<li>
<a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li>
</ul>
<p>
<b><font size=+1>Mailing-list:</font></b>
<ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul>
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<td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td>
<td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td>
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